[coreboot] Need help implementing romstage CBMEM

[Keith Hui]

Hi All,

I got some assistance from Aaron via gerrit [1] and he had me try some
changes. He also asked for my .config which is attached here.

However, the key parts are:
CONFIG_DCACHE_RAM_BASE=0xcf000
CONFIG_DCACHE_RAM_SIZE=0x01000

This is not consistent with the hard coded assumption cpu/intel/car/romstage.c:
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000

There is not enough CAR for the entire romstage stack.

Reverting to romstage_legacy and just initializing cbmem directly
there isn't taking me far either, at least I see the ramstage copy of
get_top_of_ram() get run.

Next I am going to try "modern" romstage again with an increased
CONFIG_DCACHE_RAM_SIZE, but I want to get as much info out as soon as
I can for tips.

[1] https://review.coreboot.org/20977

On Sat, Aug 12, 2017 at 10:44 PM, Keith Hui <buurin at gmail.com> wrote:
> Hi all,
>
> After reading the code for more recent Intel northbridges I think I
> have an idea on what needs to be added, so here is my attempt to bring
> 440BX to coreboot 4.7 standards:
>
> https://review.coreboot.org/20977
>
> The problem is it could not boot. The console log is attached.
>
> In short, I think I have the top of RAM value correct, but it could
> not find a place for the payload to load and the boot process is
> stuck.
>
> What am I missing?
>
> By the way, I think an unintended update for my two earlier patches
> were also pushed along with this change. How to I get them sorted out?
> [1] [2]
>
> Thanks
> Keith
>
> [1] https://review.coreboot.org/c/20868/
> [2] https://review.coreboot.org/c/20952/
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