[coreboot] x86 : Puzzles about init IDT

Nico Huber nico.huber at secunet.com
Wed Aug 16 12:33:40 CEST 2017


Hi,

On 16.08.2017 05:17, 王翔 wrote:
> The source code may have a problem when the IDT is initialized. 
> This code is located in `src/cpu/x86/16bit/entry16.inc`.
> ----------------------------------------------------------------------------------------------
> 	movw	%cs, %ax
> 	shlw	$4, %ax
> 	movw	$nullidt_offset, %bx
> 	subw	%ax, %bx
> 	lidt	        %cs:(%bx)     —> this  mybe lidtl
> 	movw	$gdtptr16_offset, %bx
> 	subw	%ax, %bx
> 	lgdtl	        %cs:(%bx)
> 
> ---------------------------------------------------------------------------------------------- 
> lidt only used for base 0-16M. 
> But nullidt located in (4G-64k) - 4G space.

I might be wrong here because I'm reading this code for the first time.
But it looks to me as if `nullidt` is not an IDT but just a null pointer
(and null limit) to zero the IDTR register (i.e. SRC in the description
of LIDT is the zero values below `nullidt:` in the source).

Nico

> This instruct must be **lidtl**
> 
> Description of LIDT
> IF Instruction is LIDT     THEN          IF OperandSize = 16               THEN                     IDTR(Limit) ← SRC[0:15];                     IDTR(Base) ← SRC[16:47] AND 00FFFFFFH;               ELSE IF 32-bit Operand Size                     THEN                          IDTR(Limit) ← SRC[0:15];                          IDTR(Base) ← SRC[16:47];                     FI;               ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)                     THEN                          IDTR(Limit) ← SRC[0:15];                          IDTR(Base) ← SRC[16:79];                     FI;          FI;     ELSE (* Instruction is LGDT *)          IF OperandSize = 16               THEN                     GDTR(Limit) ← SRC[0:15];                     GDTR(Base) ← SRC[16:47] AND 00FFFFFFH;               ELSE IF 32-bit Operand Size                     THEN                          GDTR(Limit) ← SRC[0:15];                          GDTR(Base) ← SRC[16:47];                     FI;               ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)                     THEN                          GDTR(Limit) ← SRC[0:15];                          GDTR(Base) ← SRC[16:79];                     FI;          FI; FI;
> 


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