[coreboot] About Paging, Realmode and what is going on

[Zoran Stojsavljevic]

> RAM1 stage: Since some RAM Physical mapping (AFTER *CRB*) MUST be done at
the
> beginning of the RAM stage, lookalike BIOS one (in PEI phase, I assume),
CB will proceed
> with the usual activities, set in Protected Mode. And, as we know so far
how it works, it'll
> finish this phase, looking for Payload.

Meant *MRC* (Memory Reference Code), but for some reason wrote CRB??? These
damned INTEL abbreviations will kill me...Indeed?!

On Sat, Aug 5, 2017 at 7:12 PM, ron minnich <rminnich at gmail.com> wrote:

> in the akaros virtual machine code, we set up a simple 1:1 map and start
> linux at the 64-bit entry point, at which point it builds its own page
> tables. So entering a payload in long mode is certainly possible and IMHO
> ought to be the standard on amd64 -- not that anyone cares what I think
> anyway :-)
>
> Anyway, I'm going to be working on replacing ramstage with linux again, so
> I'm not as concerted with coreboot ramstage just now ;-)
>

YUP, understood. You have to have RAM stage (before Linux), where you'll do
the first 4GB of Physical Memory Mapping (you know, MTRR init and such kind
of work), but as I see you'll try to make minimization of it:

[image: Inline image 1]

Anyway, after this you must do table init since you are, after all,
switching in 64 bit Long Mode (so tables are required). Them you switch to
64b Linux, ASAP. Well, you are trying to boot within 300 to 500 msec, I
see. It is a tough requirement, since these critical embedded applications
MUST have rebooting times virtually set to 0. Imagine unmanned plane hit by
fire, but still flying, or missile (cruse one, or you name it) hit by
fire... Not a pretty picture for the inside system control! ;-)

Zoran
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