[coreboot] Debugging MRC issues with FPS

Zoran Stojsavljevic zoran.stojsavljevic at gmail.com
Sun Sep 25 20:47:31 CEST 2016

Hello Adolfo (you are somehow known to me, isn't it that you are working
for INTEL Inside support, or maybe not)!? What does it mean _cr in your
email address (Costa Rica, isn't it)?! ;-)

Let us ask this very relevant people in INTEL Inside, who MANDATORY should
know info you are asking, since they are responsible, aren't they (INTEL
insider is asking for FSP POST codes Coreboot outsiders, which will again
ask much more relevant INTEL Insiders)??? IN -> OUT -> IN schema. Shouldn't
it be: IN -> IN schema ONLY??? :-))

Verrückt (Deutsche Sprache)?! :LOL:

Hello Stephanie,

You realize how this all strange is (the context)? *BTW, we, Coreboot
members... We should once forever know these POST codes are (you hide
inside FSPs - probably reminiscence of BIOS MRC post codes, or you tell us
all?!)? Could you, please, make this as public info to INTEL Outside?*


Could you, please, arrange what I am (in *RED*) asking for (INTEL Inside
and INTEL Outside)? You do realize why I am asking this, correct???💡

(don't touch/blame Adolfo... You should ask many questions somewhere
else... You know exactly where!)

Thank you,
Zoran Stojsavljevic, independent FREE contributor

On Sun, Sep 25, 2016 at 5:55 PM, Adolfo Sanchez <adolfo_sm_cr at hotmail.com>

> Hello
> I would like to know the best way to get information about a Failure
> related with Memory Initialization when using FPS.
> Specially when the FSPmemoryinit is being called but then the system
> hangs. POST Code 0x50
> What flags can be enable to get more information?
> Best Regards,
> Adolfo Sanchez
> --
> coreboot mailing list: coreboot at coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
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