[coreboot] CMOS post code offset
kyosti.malkki at gmail.com
Fri Sep 16 00:14:09 CEST 2016
You have confused non-volatile CMOS with SPI flash, the output of
cbfstool is about SPI flash and POST codes will not be stored there.
As AGESA platforms have some multiprocessor init in romstage, and
there is no spinlock available, CMOS reads and writes may not be
reliable. At the minimum you need to check BSP does not drive any
POSTs while it waits for APs, but as this happens in vendorcode those
POSTs would not be recorded anyway in CMOS.
If you still want the offset:
With USE_OPTION_TABLE=y, renaming in cmos.layout user_data to
cmos_post_offset might do it.
With USE_OPTION_TABLE=n same place, set CMOS_POST_OFFSET=91 (=728/8).
You probably get error message about invalid checksum in the log if
you use that offset, but that should not trigger loading of defaults.
You will also want someone to call cmos_post_log() at boot to show the
previously stored POST, I can't tell if DRIVERS_ELOG works with AGESA
Hope this helps,
More information about the coreboot