[coreboot] POST 0xFFFF

Riko Ho antonius.riko at gmail.com
Mon Oct 31 02:26:14 CET 2016


Everyone,

I got POST 0xFFFF then loop, and UART = 00
I have rewritten the ich7_enable_lpc function, and the complete
romstage.c attached, what do I miss here ? Does enable_lapic();
function depend to the board or it can run on 946 even it's written
for 945?

static void ich7_enable_lpc(void)
{
    // Enable Serial IRQ
    pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
    // Set COM1/COM2 decode range
    pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
    // Enable COM1
    //pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
        pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); //from
sudo lspci -xxx -s 0:1F.0
    // Enable SuperIO Power Management Events
    //pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
        //pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700);
          pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84,
0x003C0801);//from sudo lspci -xxx -s 0:1F.0, Idwer suggestion
}

 bianchi at bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0
>> [sudo] password for bianchi:
>> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC
>> Interface Bridge (rev 01)
>> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00
>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21
>> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
>> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00
>> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00
>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00
>> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00
>> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00
>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00
>> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00
>> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00
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