[coreboot] Stops at 0xD2
Riko Ho
antonius.riko at gmail.com
Sat Oct 29 03:00:22 CEST 2016
Stefan,
Yes I'm using the right driver, I'm not sure if that driver is
doing what we need to run this chip, I didn't make it, but I'll improve
it if it's needed,
I took this register data awhile ago , and I have some discussions at
IRC to have a look on register 0x23...
So far I can't get 8718 on my POST card
Which register is related with UART setting ? I'll find out on datasheet
anyway, but it would be very nice if you have a clues...
Is it :
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3
?
How can I retrieve that value to my POST card for debugging and see what
it's saying to us ?
Cheers,
RH
Please have a look:
Probing for ITE Super I/O (init=standard) at 0x2e...
Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e
*Register dump:**
**idx 20 21 22 23 24 2b**
**val 87 18 01 10 00 00**
**def 87 18 01 00 00 00*
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 00 00 00 00 00 80
def 00 03 f0 06 02 00 00
*LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1 f2 f3
val 01 03 f8 04 00 50 00 7f
def 00 03 f8 04 00 50 00 7f*
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1 f2 f3
val 01 02 f8 03 00 50 00 7f
def 00 02 f8 03 00 50 00 7f
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6
val 01 02 90 00 00 00 00 00 2a 00 80 00 ff
def 00 02 90 02 30 09 00 00 00 00 00 NA NA
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 68
def 01 00 60 00 64 01 02 00
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3
b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc e0 e1 e2 e3
e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff
val 00 10 00 01 08 80 1f 00 00 08 00 00 00 00 00 00 38 00 80 00 00 00
00 00 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 01 08 00 00 00 00
00 00 00 00 10 00 00 00 14 00 00 00 2b 01 00 06 ff 00 00 00
def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00
00 00 00 00 00 00 00 00 01 00 00 40 00 00 01 00 00 40 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 00 00
LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 00 00 00 06
def 00 03 10 0b 00
Environment controller (0x0295)
Register dump:
idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15
16 17 18 19 1a 1b 1c 1d 20 21 22 23 24 25 26 27 28 29 2a 2b 30 31 32
33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 50 51 52 53
54 56 57 58 59 5b 5c 5d 5e 5f 60 61 62 63 64 65 68 69 6a 6b 6c 6d 70
71 72 73 74 75 80 81 82 83 88 89 8a 8b 8c 8d 8e 8f 90 91 92 94 95 96
a0 a1 a2 a3 a4 a5 a6
val 13 14 ff 02 ff ff fb 00 00 80 00 09 07 35 ff ff ff ff 00 77 d0 82
80 3f 01 ff ff ff ff ff 4b bc cd ba 4c b3 6c b8 c5 1b 7f 22 ff ff ff
ff ff ff ff ff 19 37 ff ff 3a 2d ff ff 5a 7f 5a 7f 5a 7f ff 1c 7f 7f
7f e6 e6 90 e6 12 80 00 00 00 05 30 7f 19 28 82 05 27 7f 37 38 82 7f
7f 7f 00 00 7f 00 00 00 00 00 00 00 00 00 00 02 00 ff 00 00 ff 00 00
00 00 00 00 00 00 00
def 18 00 00 00 00 00 00 00 00 80 40 09 00 NA NA NA NA NA NA 07 50 MM
MM MM NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 7f 7f
7f 00 00 90 00 12 00 00 00 00 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f 7f
7f 7f 00 00 7f NA NA NA NA 00 00 00 00 00 00 02 00 ff 00 00 ff 00 00
00 00 00 00 00 00 00
BRAM (0x0000)
=====
Probing for ITE Super I/O (init=standard) at 0x4e...
Failed. Returned dat
On 29/10/2016 6:56 AM, Stefan Reinauer wrote:
> * Riko Ho <antonius.riko at gmail.com> [161026 03:36]:
>> Everyone,
>>
>> I tried to initialize UART on IT8718F and it stopped at 0xD2...
>> Here's the complete function, any clues ?
> Yes, there is a halt() right after the post_code(0xd2); so that is where
> your last post code is coming from.
>
> use superiotool (from coreboot/util) to dump the superio registers on a
> running system and compare them with what you write in there and the
> data sheet.
>
> Are you sure you are using the correct SuperIO driver?
>
> Stefan
>
>> Cheers
>> ===============
>> void mainboard_romstage_entry(unsigned long bist)
>> {
>> int s3resume = 0, boot_mode = 0;
>>
>> if (bist == 0)
>> enable_lapic();
>>
>> ich7_enable_lpc();
>> post_code(0xD1);
>> /* Enable SuperIO PM */
>> //lpc47m15x_enable_serial(PME_DEV, 0x680);
>> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //enable_dev(SERIAL_DEV);
>> //ite_conf_clkin();//needs a parameter, what is it ?
>>
>> /*
>> 04:24:31 AM) idwer: 24 or 48 MHz?
>>
>> (04:25:18 AM) idwer: how do you find out? run superiotool when
>> having booted with the vendor bios, and look at register
>> CR23
>> */
>> //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
>> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
>>
>>
>> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");
>> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
>> it8718f_disable_reboot(GPIO_DEV);
>> /* Set up the console */
>> console_init();
>> post_code(0xD2);
>> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
>> halt();
>> post_code(0xD3);
>>
>>
>>
>> /* Halt if there was a built in self test failure */
>> report_bist_failure(bist);
>>
>> if (MCHBAR16(SSKPD) == 0xCAFE) {
>> printk(BIOS_DEBUG, "soft reset detected.\n");
>> boot_mode = 1;
>> }
>>
>> /* Perform some early chipset initialization required
>> * before RAM initialization can work
>> */
>> i945_early_initialization();
>> post_code(0xD4);
>> s3resume = southbridge_detect_s3_resume();
>>
>> /* Enable SPD ROMs and DDR-II DRAM */
>> enable_smbus();
>>
>> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
>> dump_spd_registers();
>> #endif
>>
>> sdram_initialize(s3resume ? 2 : boot_mode, NULL);
>>
>> /* Perform some initialization that must run before stage2 */
>> early_ich7_init();
>>
>> /* This should probably go away. Until now it is required
>> * and mainboard specific
>> */
>> rcba_config();
>>
>> /* Chipset Errata! */
>> fixup_i945_errata();
>>
>> /* Initialize the internal PCIe links before we go into stage2 */
>> i945_late_initialization(s3resume);
>> }
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>>
--
*/*===
Kind regards,
Riko Ho
===*/ *
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