[coreboot] Stops at 0xD2

[Riko Ho]

Thanks for the reply....
Let me step it :

1.
I got this when I compile it :
build/auto.conf:1974:warning: override: reassigning to symbol
CONSOLE_SERIAL_TEGRA210_UART_CHOICES

2. I requested to have that halt() added after console_init().
===>Ok, I will move it....

3. Looks like other boards
with same superio use call ite_kill_watchdog(), I don't know what
it8718f_disable_reboot() does.
===> I have no idea as well, I followed on example from the board
which used it8718f

4. There was also suggestion to dump superio ID register on POST
display to make sure LPC bus communication to superio works, but I did
not hear back from that experiment.
===> can you tell me how to do that ?

Cheers

On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki <kyosti.malkki at gmail.com> wrote:
> The information missing from the mail is I requested to have that halt()
> added after console_init().
>
> Also at least it was previously reported system was in a periodic reset-loop
> regardless of the halt() there, so sn active watchdog may be involved here.
> Looks like other boards
> with same superio use call ite_kill_watchdog(), I don't know what
> it8718f_disable_reboot() does.
>
> There was also suggestion to dump superio ID register on POST display to
> make sure LPC bus communication to superio works, but I did not hear back
> from that experiment.
>
> Kyösti
>
> On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho <antonius.riko at gmail.com> wrote:
>>
>> Everyone,
>>
>> I tried to initialize UART on IT8718F and it stopped at 0xD2...
>> Here's the complete function, any clues ?
>>
>> Cheers
>> ===============
>> void mainboard_romstage_entry(unsigned long bist)
>> {
>>     int s3resume = 0, boot_mode = 0;
>>
>>     if (bist == 0)
>>         enable_lapic();
>>
>>     ich7_enable_lpc();
>>         post_code(0xD1);
>>     /* Enable SuperIO PM */
>>     //lpc47m15x_enable_serial(PME_DEV, 0x680);
>>     //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>>         //enable_dev(SERIAL_DEV);
>>         //ite_conf_clkin();//needs a parameter, what is it ?
>>
>>         /*
>>         04:24:31 AM) idwer: 24 or 48 MHz?
>>
>>     (04:25:18 AM) idwer: how do you find out? run superiotool when
>> having booted with the vendor bios, and look at            register
>> CR23
>>          */
>>     //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
>>         ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
>>
>>
>>         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
>>         //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n");
>>         //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
>>     it8718f_disable_reboot(GPIO_DEV);
>>     /* Set up the console */
>>     console_init();
>>         post_code(0xD2);
>>         printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n");
>>         halt();
>>         post_code(0xD3);
>>
>>
>>
>>     /* Halt if there was a built in self test failure */
>>     report_bist_failure(bist);
>>
>>     if (MCHBAR16(SSKPD) == 0xCAFE) {
>>         printk(BIOS_DEBUG, "soft reset detected.\n");
>>         boot_mode = 1;
>>     }
>>
>>     /* Perform some early chipset initialization required
>>      * before RAM initialization can work
>>      */
>>     i945_early_initialization();
>>         post_code(0xD4);
>>     s3resume = southbridge_detect_s3_resume();
>>
>>     /* Enable SPD ROMs and DDR-II DRAM */
>>     enable_smbus();
>>
>> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
>>     dump_spd_registers();
>> #endif
>>
>>     sdram_initialize(s3resume ? 2 : boot_mode, NULL);
>>
>>     /* Perform some initialization that must run before stage2 */
>>     early_ich7_init();
>>
>>     /* This should probably go away. Until now it is required
>>      * and mainboard specific
>>      */
>>     rcba_config();
>>
>>     /* Chipset Errata! */
>>     fixup_i945_errata();
>>
>>     /* Initialize the internal PCIe links before we go into stage2 */
>>     i945_late_initialization(s3resume);
>> }
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>
>