[coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95

James_Lee james_lee at lannerinc.com
Wed Oct 19 12:58:51 CEST 2016


Hello All,

   My platform is Intel camelback CRB, I use coreboot +intel FSP,

But hang on 7a or 95, please see below log, and attach .config,

I have enable serial irq conutine mode, have some guys know 

the root cause? Thanks.

 

Best Regards

-James 

 

 

Hide devices in Bus:255

Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry
point: 7F7417E7

FSP Notification Handler Returns : 0x00000000

FSP Got Notification. Notification Value : 0x00000040

FSP Ready To Boot ...

Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B

Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry
point: 7F7966F7

Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry
point: 7F79991A

IioLateInitialize ReadyToBoot Callback

OnExitBootServices..

IioInit Late Secure the Platform (TXT)..

Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry
point: 7F766B1E

Hiding ME Devices

Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry
point: 7F7727C4

MP ReadyToBootEvent()

:: Set LOCK bit in PACKAGE_RAPL_LIMIT with value = 80078150

:: Set LOCK bit in CSR_SAPMCTL with value = B8002024

:: Set LOCK bit in CSR_DRAM_PLANE_POWER_LIMIT with value = 80000000

:: Set LOCK bit in P_STATE_LIMITS_PCU_FUN0_REG with value = 800000FF

:: Set LOCK bit in CSR_DESIRED_CORES_PCU_FUN1_REG with value = 80000000

 

Done Write MAILBOX_BIOS_CMD_WRITE_PCU_MISC_CONFIG, data = 800002, SETUP
Pl2SafetyNetEnable = 1

:: Read BIOS_MAILBOX_DATA_PCU_FUN1_REG back, data = 800002

:: Debug PpmSetBiosInitDone Read Data: 00000606

 

Detected 16 CPU threads

Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry
point: 7F7190F5

PciERWORegInit() Start

PciERWORegInit() End

ThermalLockDown() Start

ThermalLockdown() - ThermalBaseB = 00000004

ThermalBaseB not set!!

BDX-DE MCP PMSYNC enable = 1 

InstallPchThermalLevelsProtocol()

ASSERT DUMP:

-> EBP:0x7F0FDE60  EIP:0x7F719305

-> EBP:0x7F0FDEBC  EIP:0x7F718D2D

-> EBP:0x7F0FDEF4  EIP:0x7F7190FD

-> EBP:0x7F0FDF30  EIP:0x7F7FA29B

-> EBP:0x7F0FDF5C  EIP:0x7F7F309B

-> EBP:0x7F0FDF84  EIP:0x7F7F2DC9

-> EBP:0x7F0FE8EC  EIP:0xFFEB2239

-> EBP:0x7F0FF24C  EIP:0xFFEB5584

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