[coreboot] Nehalem not booting with two ram sticks

[Zoran Stojsavljevic]

Hello Charlotte ++,

Forgive me/apologies for my ignorance in some parts... I would like to ask
few questions since I am not clear on some data here.

On Tue, Nov 22, 2016 at 8:30 PM, Charlotte Plusplus <
pluspluscharlotte at gmail.com> wrote:

> I have had similar issues with Corsair ram on the W520 recently: sometimes
> not booting at all, sometimes being unstable (in memest) after a succesfull
> raminit.
>
> The only way I could get the 4 dimms to work was to hardcode some SPDs, or
> set the MCU to a much slower speed.
>

As I know (and knew) MCU stands for MicroCode Unit (INTEL terminology), or
Memory Controller Unit (common terminology), and I am sure you do refer to
later, since to former this does not make too many (not at all) sense (to
me, at least).

If MCU is former, could you, please, explain the following: *"set the MCU
to a much slower speed"*?
If MCU is later, could you, please, explain how you did this in IVB
Coreboot code (since this might be beneficial to Federico's attempts)?


> Like you, I found removing even 1 stick did help a lot: the raminit
> succeeded much more frequently as a higher MCU, even if this MCU still
> lower than the one the RAM is rated for, or that worked in the factory bios.
>
> I tried using the MRC blob to compare the timings, but I must have done
> something wrong in my code as it didn't work at all.
>

Here I understood that you tried to compare IVB raminit.c source code with
MRC algorithm, embedded in BIOS itself. And I have here one ignorant
question: what is the difference between IVB (I assumed in this case SNB
(tock), since I could not find IVB (tick) in rc/northbridge/intel/)
raminit.c source code and MRC from IVB BIOS (there MUST be some difference,
it is obvious, doesn't it)?

My guess is something is really wrong in the raminit code. I read up too
> much specs and code for no result, so I just gave up on this.
>

This is exactly the main point! And the main question here is the
following: who wrote raminit.c code, and does this person did it using
parts of IVB/SNB MRC source code? In other words, was this person member of
SNB BIOS team from INTEL CCG?

This is much more question directed to INTEL people (IOTG and CCG)
observing this thread. Also to Ron (Minnich). Or anybody else from Coreboot
knowing the answer.

Hopefully more people getting similar problems will mean the MRC will be
> added back as an option next to the native raminit. This would facilite
> comparison on all boards, and identification of whatever bug there may be.
> (imagine figuring out native video init issues if there was no way to use a
> VGA option rom)
>

This is also a good point. I need clarification on the following:* "...will
mean the MRC will be added back as an option next to the native raminit"*.
Do you mean to have IVB/SNB MRC binary blob with defined APIs to be used as
alternative to IVB/SNB raminit.c, since I am certain INTEL will not allow
to have complete MRC added in Coreboot as source code (never was, never
will be)?

Thank you (and everybody else) in advance for clarification (answers to
these questions),
Zoran

Charlotte
>
> On Tue, Nov 22, 2016 at 8:22 AM, Andrey Korolyov <andrey at xdel.ru> wrote:
>
>> On Tue, Nov 22, 2016 at 3:35 PM, Federico Amedeo Izzo
>> <federico.izzo42 at gmail.com> wrote:
>> > Hello,
>> >
>> > I have a problem with my ThinkPad X201 (nehalem)
>> >
>> > I have two sticks of Samsung 4GB 2Rx8 PC3-10600S (1333MHz)
>> > When i use only one of them in one of the two slots, the computer boots
>> > fine,
>> > but when i use both of them in the two slots, the computer doesn't boot,
>> > the screen doens't even turn on.
>> >
>> > I dumped the logs via EHCI but they seem normal, in fact both the
>> > working combination and the broken one make 34 or so iterations of
>> > Timings dumping,
>> > but then the working conf. start booting, while the broken one freezes
>> > without printing error messages on the EHCI.
>> >
>> > I have tried adding more `printk` calls in
>> > `src/northbridge/intel/nehalem/raminit.c`
>> > but ended up in a brick, probably because i slowed down the
>> > initialization too much.
>> >
>> > I attach three EHCI logs:
>> > - the first stick in the first slot: working
>> > - the second stick in the second slot: working
>> > - both stick inserted: not working
>> >
>> > Also i find difficult to understand the code in `raminit.c` of nehalem
>> > because it lacks almost completely of comments, with respect to
>> > raminit.c of sandybridge for example.
>>
>> I`ve seen simular issue on my x201(t), the workaround could be a
>> hardcoded SPD limitation from above for memory clock speed. Using
>> different memory sticks (Kingstons rather than Samsungs) is 'solving'
>> problem as well. I`ve not paid necessary attention to the problem at
>> the time, so if you have some spare cycles, you could possibly want to
>> figure out right SPD settings. The simplest way is to use decode-dimms
>> from i2c-tools or CPU-z and to compare vendor`s settings with single-
>> and dual-dimm setups and coreboot`s with a single dimm.
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
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>
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