[coreboot] More details about ram issues

[Nico Huber]

Hi Charlotte,

On 11.11.2016 08:14, Charlotte Plusplus wrote:
> So I did many more tests today (more than 6h, and flashing around 30
> times), with SPD settings hardcoded into raminit, and without the mrc cache
> interfering.

thanks for the analysis and summing this up.

> 
> TLDR: coreboot tries to increase the frequency without increasing the
> voltage, and that doesn't work for all memory.
> 
> Basically, with the problematic ram sticks, I can boot perfectly fine at
> DDR3-1866 speed, but even the slower setting 11-11-11-31 gives errors on
> the memtest. This is inconsistent with information I found about my memory
> from its SPD information, and from other people who overclock this exact
> same memory.
> 
> Even at 10-10-10-27, I still get errors at DDR3-1600 speeds. Far fewer than
> before, but some errors sill.
> 
> After reading more about XMP and SPD, it is my understanding that :
>  - JEDEC specs stop at 1600, and after that XMP is required
>  - even before 1600, XMP also offers profiles, and they are not optional:
> some memory is otherwise unable to work at its advertised speed

This would mean the memory is just broken. But that's what I suspect of
any memory that's supposed to run out of spec.

>  - XMP profiles are some kind of overclocking: they usually require
> adjusting the voltage, to deal with this increased speed

Not kind of overclocking, simply overclocking. There's only one voltage
specified for DDR3, IIRC.

>  - in XMP profile bytes, voltage increase information is given precisely
>  - nowhere in the code I saw anything increasing the voltage, while XMP
> requires that
> 
> I conclude that while there may be errors in selecting the SPD settings,
> even if the SPD is manually corrected with known-good settings, or if
> overshooting with very generous latencies, some errors do remain as the ram
> is being asked to operate outside its voltage specifications (given the
> frequency)
> 
> 1.5V is a JEDEC spec, but RAM is advertised based on the information
> contained in the XMP profiles, which at the moment do not seem fully
> supported.

JEDEC is the standard. If the XMP support is half-baked it should be
disabled by default. Maybe we should even put a warning in the log if we
encounter an XMP profile with anything else than 1.5V (if it's common
that those DIMMs are broken ex factory).

> 
> I do not know how to adjust the voltage (it should require talking to the
> IMC of the CPU)  but I think that as soon as this is done, stability should
> improve.
> 
> If someone can propose a patch doing that (either using the voltage read
> from SPD, or by manually entering voltage information), I will be happy to
> test it.

Depending on the board the voltage might not be configurable at all. Why
should it be if there is only one voltage defined in the standard?

> 
> For now, I urge caution when operating even at DDR-1866 frequencies. Most
> boards do set up 933 as their max_mem_clock_mhz. It is not very prudent to
> do that until the voltage situation can be solved.

If the board can work at that frequency, that's just fine. If the
voltage is a problem, it's due to the memory module. IMHO, the rule
should be to ignore SPD frequency settings that include an out of spec
voltage.

If you want to do further testing, you can try to find out which com-
binations of processor and DIMMs work with the Vendor BIOS or the MRC
blob (I wouldn't expect that it supports non-JEDEC stuff, but it would
be nice to know if something can be fixed in coreboot easily).

Nico