[coreboot] More details about ram issues
Charlotte Plusplus
pluspluscharlotte at gmail.com
Tue Nov 8 08:15:31 CET 2016
Hello
I have done further ram testing.
My first guess was to disable the XMP code - it didn't help, but I may have
done things wrong as I was trying with a normal and a fallback mode to try
more combinations of options, and apparently the ram settings are cached
and shared between normal and fallback, even when max_mem_clock_mhz differ.
That's not a good thing when working on ram issues, so I wonder, is there
any way to manually invalidate that mrc cache during tests?? (I almost want
to comment the function in raminit.c) Since I don't have a USBDEBUG yet,
I go to a linux shell to check the cbmem output between tests. So anything
I can type to disable the mrc cache would do.
Alternatively, a really nice thing to have would be a nvram option to pass
max_mem_clock_mhz without having to recompile, and invalidate this cache if
the settings do not match, to cover cases like this one. Also,
overclockers would love that. So this option could even be used to pass
custom SPD timings, as some bios do. It would require more thinking on what
to do and how, but it looks like a nice feature to me. Would it be
acceptable to add that to coreboot?
Anyway, I tried to downclock at various frequencies:
- 666 Mhz: CAS 7-7-7-20 : all sticks work, individually and together
- 800 Mhz: CAS 9-9-9-24: 1 stick doesn't work, the others do, but I still
get errors during the memtest step 8.
I regret it is not possible to manually enter the right SPD information
that I know to work: 11-11-11-29 for DDR3-2000, 11-11-11-31 for DDR3-2133 -
and something slightly larger for DDR3-1600. So I have DDR3-2133 sticks
that I am forced to run at DDR3-1333 speeds because otherwise the selected
SPD settings make everything unstable :-(
If only I could slightly increase the latency, I could run at least at
DDR3-1600 speeds with 0 error in memtest. I'm thinking of tweaking
dram_find_common_params with:
ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS) +X;
and manually trying X=1, X=2 etc. until I can finally have memtest running
without error.
Would there be any issues with that? Any better idea?
Here is an extract from the log:
find_current_mrc_cache_local: No valid MRC cache found.
Revision : 11
Type : b
Key : 3
Banks : 8
Capacity : 4 Gb
Supported voltages : 1.35V 1.5V
SDRAM width : 8
Bus extension : 0 bits
Bus width : 64
Optional features : DLL-Off_mode RZQ/7 RZQ/6
Thermal features : PASR ext_temp_range
Thermal sensor : no
Standard SDRAM : yes
Rank1 Address bits : normal
DIMM Reference card: B
Manufacturer ID : 9e02
Part number : CMSX16GX3M2B2133
Not a DDR3 SPD!
Row addr bits : 16
Column addr bits : 10
Number of ranks : 2
DIMM Capacity : 8192 MB
CAS latencies : 6 7 8 9 10 11
tCKmin : 1.000 ns
tAAmin : 10.250 ns
tWRmin : 15.000 ns
tRCDmin : 10.250 ns
tRRDmin : 6.500 ns
tRPmin : 10.250 ns
tRASmin : 29.000 ns
tRCmin : 39.375 ns
tRFCmin : 260.750 ns
tWTRmin : 7.625 ns
tRTPmin : 8.375 ns
tFAWmin : 30.875 ns
channel[0] rankmap = 0x3
Not a DDR3 SPD!
Not a DDR3 SPD!
Starting RAM training (0).
PLL busy... PLL busy... PLL busy...done
MCU frequency is set at : 800 MHz
Selected DRAM frequency: 800 MHz
Minimum CAS latency : 9T
Selected CAS latency : 9T
Selected CWL latency : 7T
Selected tRCD : 9T
Selected tRP : 9T
Selected tRAS : 24T
Selected tWR : 12T
Selected tFAW : 25T
Selected tRRD : 6T
Selected tRTP : 7T
Selected tWTR : 7T
Selected tRFC : 209T
XOVER CLK [c14] = 3000000
XOVER CMD [320c] = 24000
XOVER CLK [d14] = 0
XOVER CMD [330c] = 4000
DBP [4000] = 187999
RAP [4004] = cc197476
OTHP [400c] = a08b4
ODT stretch [400c] = 0
ODT stretch [400c] = a08b4
REFI [4298] = 6cd11860
SRFTP [42a4] = 41f88200
DBP [4400] = 187999
RAP [4404] = cc197476
OTHP [440c] = a08b4
ODT stretch [440c] = 0
ODT stretch [440c] = a08b4
REFI [4698] = 6cd11860
SRFTP [46a4] = 41f88200
Done dimm mapping
MCU frequency is set at : 800 MHz
XOVER CLK [c14] = 3000000
XOVER CMD [320c] = 24000
XOVER CLK [d14] = 0
XOVER CMD [330c] = 4000
DBP [4000] = 187999
RAP [4004] = cc197476
OTHP [400c] = a08b4
ODT stretch [400c] = 0
ODT stretch [400c] = a08b4
REFI [4298] = 6cd11860
SRFTP [42a4] = 41f88200
DBP [4400] = 187999
RAP [4404] = cc197476
OTHP [440c] = a08b4
ODT stretch [440c] = 0
ODT stretch [440c] = a08b4
REFI [4698] = 6cd11860
SRFTP [46a4] = 41f88200
Done dimm mapping
For 666:
Trying stored timings.
Starting RAM training (1).
PLL busy... PLL busy...done
MCU frequency is set at : 666 MHz
XOVER CLK [c14] =
f000000
XOVER CMD [320c] = 4024000
XOVER CLK [d14] = 0
XOVER CMD [330c] = 4000
DBP [4000] = 146777
RAP [4004] = ca156465
OTHP [400c] = a0690
ODT stretch [400c] = 0
REFI [4298] = 5aae1450
SRFTP [42a4] = 41f97200
DBP [4400] = 146777
RAP [4404] = ca156465
OTHP [440c] = a0690
ODT stretch [440c] = 0
ODT stretch [440c] = a0690
REFI [4698] = 5aae1450
SRFTP [46a4] = 41f97200
Done dimm mapping
The timestamps are:
0:1st timestamp 1,789
1:start of rom stage 59,405 (57,616)
2:before ram initialization 1,768,793 (1,709,388)
3:after ram initialization 1,818,226 (49,432)
4:end of romstage 1,828,566 (10,340)
8:starting to load ramstage 1,833,895 (5,329)
15:starting LZMA decompress (ignore for x86) 1,833,926 (30)
16:finished LZMA decompress (ignore for x86) 1,848,244 (14,317)
9:finished loading ramstage 1,848,254 (9)
10:start of ramstage 3,186,861 (1,338,607)
30:device enumeration 3,186,890 (29)
40:device configuration 3,195,250 (8,359)
50:device enable 3,207,057 (11,806)
60:device initialization 3,207,563 (506)
70:device setup done 3,378,965 (171,402)
75:cbmem post 3,378,968 (3)
80:write tables 3,378,972 (4)
90:load payload 3,399,267 (20,294)
15:starting LZMA decompress (ignore for x86) 3,399,430 (163)
16:finished LZMA decompress (ignore for x86) 3,413,428 (13,998)
99:selfboot jump 3,413,449 (21)
Full cbmem attached from various attempts (when I have more than 1 stick in
place, the log is truncated)
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coreboot-4.5-103-g25445dc-charlotte1 Mon Oct 31 19:29:56 UTC 2016 romstage starting...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
Back from sandybridge_early_initialization()
SMBus controller enabled.
CPU id(306a9): Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz
AES supported, TXT supported, VT supported
PCH type: QM67, device id: 1c4f, rev id 5
Intel ME early init
Intel ME firmware is ready
ME: Requested 8MB UMA
Starting native Platform init
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset 2fec0 size 10000
find_current_mrc_cache_local: No valid MRC cache found.
Revision : 11
Type : b
Key : 3
Banks : 8
Capacity : 4 Gb
Supported voltages : 1.35V 1.5V
SDRAM width : 8
Bus extension : 0 bits
Bus width : 64
Optional features : DLL-Off_mode RZQ/7 RZQ/6
Thermal features : PASR ext_temp_range
Thermal sensor : no
Standard SDRAM : yes
Rank1 Address bits : normal
DIMM Reference card: B
Manufacturer ID : 9e02
Part number : CMSX16GX3M2B2133
Not a DDR3 SPD!
Row addr bits : 16
Column addr bits : 10
Number of ranks : 2
DIMM Capacity : 8192 MB
CAS latencies : 6 7 8 9 10 11
tCKmin : 1.000 ns
tAAmin : 10.250 ns
tWRmin : 15.000 ns
tRCDmin : 10.250 ns
tRRDmin : 6.500 ns
tRPmin : 10.250 ns
tRASmin : 29.000 ns
tRCmin : 39.375 ns
tRFCmin : 260.750 ns
tWTRmin : 7.625 ns
tRTPmin : 8.375 ns
tFAWmin : 30.875 ns
channel[0] rankmap = 0x3
Not a DDR3 SPD!
Not a DDR3 SPD!
Starting RAM training (0).
PLL busy... PLL busy... PLL busy...done
MCU frequency is set at : 800 MHz
Selected DRAM frequency: 800 MHz
Minimum CAS latency : 9T
Selected CAS latency : 9T
Selected CWL latency : 7T
Selected tRCD : 9T
Selected tRP : 9T
Selected tRAS : 24T
Selected tWR : 12T
Selected tFAW : 25T
Selected tRRD : 6T
Selected tRTP : 7T
Selected tWTR : 7T
Selected tRFC : 209T
XOVER CLK [c14] = 3000000
XOVER CMD [320c] = 24000
XOVER CLK [d14] = 0
XOVER CMD [330c] = 4000
DBP [4000] = 187999
RAP [4004] = cc197476
OTHP [400c] = a08b4
ODT stretch [400c] = 0
ODT stretch [400c] = a08b4
REFI [4298] = 6cd11860
SRFTP [42a4] = 41f88200
DBP [4400] = 187999
RAP [4404] = cc197476
OTHP [440c] = a08b4
ODT stretch [440c] = 0
ODT stretch [440c] = a08b4
REFI [4698] = 6cd11860
SRFTP [46a4] = 41f88200
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 2
PCI(0, 0,
*** Log truncated, 184195 characters dropped. ***
Relocate MRC DATA from fefff5e0 to 7ffdc000 (1440 bytes)
CBMEM entry for DIMM info: 0x7fffe880
TPM initialization.
Found TPM ST33ZP24 by ST Microelectronics
TPM: command 0x99 returned 0x0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'normal/ramstage'
CBFS: Found @ offset 94180 size 1295f
Capability: type 0x01 @ 0x50
Capability: type 0x0a @ 0x58
coreboot-4.5-103-g25445dc-charlotte1 Mon Oct 31 19:29:56 UTC 2016 ramstage starting...
Moving GDT to 7fffe660...ok
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 0
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 1
PCI: 00:1c.7: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 0
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 1
PCI: 00:1c.7: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0154] ops
Normal boot.
PCI: 00:00.0 [8086/0154] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0151] disabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0166] enabled
PCI: 00:04.0 [8086/0153] enabled
PCI: 00:16.0 [8086/1c3a] ops
PCI: 00:16.0 [8086/1c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.2 [8086/1c3c] disabled No operations
PCI: 00:16.3: Disabling device
PCI: 00:16.3 [8086/1c3d] disabled No operations
PCI: 00:19.0 [8086/1502] enabled
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1c2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1c20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0: Disabling device
PCI: 00:1c.0: check set enabled
PCH: Remap PCIe function 1 to 0
PCI: 00:1c.1 [8086/0000] bus ops
PCI: 00:1c.1 [8086/1c12] enabled
PCH: Remap PCIe function 2 to 0
PCI: Static device PCI: 00:1c.2 not found, disabling it.
PCH: Remap PCIe function 3 to 0
PCI: 00:1c.3 [8086/0000] bus ops
PCI: 00:1c.3 [8086/1c16] enabled
PCH: Remap PCIe function 4 to 0
PCI: 00:1c.4 [8086/0000] bus ops
PCI: 00:1c.4 [8086/1c18] enabled
PCI: 00:1c.5: Disabling device
PCH: Remap PCIe function 6 to 0
PCI: Static device PCI: 00:1c.6 not found, disabling it.
PCH: Remap PCIe function 7 to 0
PCH: RPFN 0x76543210 -> 0x64d3210f
PCH: PCIe map 1c.0 -> 1c.7
PCH: PCIe map 1c.1 -> 1c.0
PCH: PCIe map 1c.2 -> 1c.1
PCH: PCIe map 1c.3 -> 1c.2
PCH: PCIe map 1c.4 -> 1c.3
PCH: PCIe map 1c.6 -> 1c.4
PCH: PCIe map 1c.7 -> 1c.6
PCI: Static device PCI: 00:1c.6 not found, disabling it.
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1c26] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1c4f] enabled
PCI: 00:1f.2 [8086/0000] ops
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
PCI: 00:1f.2 [8086/1c01] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1c22] enabled
PCI: 00:1f.6 [8086/1c24] enabled
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [168c/0030] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpointASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.0 took 344 usecs
PCI: 00:1c.2 scanning...
do_pci_scan_bridge for PCI: 00:1c.2
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:1c.2 took 82 usecs
PCI: 00:1c.3 scanning...
do_pci_scan_bridge for PCI: 00:1c.3
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [1180/e823] enabled
PCI: 03:00.1 [1180/e232] enabled
PCI: 03:00.2 [1180/e852] enabled
PCI: 03:00.3 [1180/e832] enabled
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.3 took 1193 usecs
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
PNP: 00ff.1 enabled
PNP: 0c31.0 enabled
recv_ec_data: 0x38
recv_ec_data: 0x41
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x38
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
recv_ec_data: 0x00
recv_ec_data: 0x12
EC Firmware ID 8AHT38WW-3.20, Version 0.01C
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x00
recv_ec_data: 0x10
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x20
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x30
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x00
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0xa7
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0xc2
recv_ec_data: 0x70
PNP: 00ff.2 enabled
scan_lpc_bus for PCI: 00:1f.0 done
scan_bus: scanning of bus PCI: 00:1f.0 took 5980 usecs
PCI: 00:1f.3 scanning...
scan_smbus for PCI: 00:1f.3
smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_smbus for PCI: 00:1f.3 done
scan_bus: scanning of bus PCI: 00:1f.3 took 206 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 9208 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 9297 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 10214 exit 0
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
More than one caller of pci_ehci_read_resources from PCI: 00:1a.0
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.2 read_resources bus 2 link: 0
PCI: 00:1c.2 read_resources bus 2 link: 0 done
PCI: 00:1c.3 read_resources bus 3 link: 0
PCI: 00:1c.3 read_resources bus 3 link: 0 done
PCI: 00:1d.0 EHCI BAR hook registered
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI: 00:1f.3 read_resources bus 1 link: 0
PCI: 00:1f.3 read_resources bus 1 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: acac
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:01.0
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
PCI: 00:04.0
PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
PCI: 00:16.0
PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 00:1a.0
PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:1c.7
PCI: 00:1c.0 child on link 0 PCI: 01:00.0
PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:1c.3 child on link 0 PCI: 03:00.0
PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 03:00.1
PCI: 03:00.1 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 03:00.2
PCI: 03:00.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 03:00.3
PCI: 03:00.3 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 10
Unknown device path type: 0
Unknown device path type: 0
resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10
Unknown device path type: 0
resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14
Unknown device path type: 0
resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18
PCI: 00:1c.5
PCI: 00:1c.4
PCI: 00:1c.6
PCI: 00:1d.0
PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1f.0 child on link 0 PNP: 00ff.1
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
PNP: 00ff.1
PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
PNP: 0c31.0
PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
PNP: 00ff.2
PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
PCI: 00:1f.2
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
PCI: 00:1f.3 child on link 0 I2C: 01:54
PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:5c
I2C: 01:5d
I2C: 01:5e
I2C: 01:5f
PCI: 00:1f.6
PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
Unknown device path type: 0
18 * [0x0 - 0xfff] io
PCI: 00:1c.3 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 1c * [0x0 - 0xfff] io
PCI: 00:02.0 20 * [0x1000 - 0x103f] io
PCI: 00:19.0 18 * [0x1040 - 0x105f] io
PCI: 00:1f.2 20 * [0x1060 - 0x107f] io
PCI: 00:1f.2 10 * [0x1080 - 0x1087] io
PCI: 00:1f.2 18 * [0x1088 - 0x108f] io
PCI: 00:1f.2 14 * [0x1090 - 0x1093] io
PCI: 00:1f.2 1c * [0x1094 - 0x1097] io
DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 01:00.0 30 * [0x20000 - 0x2ffff] mem
PCI: 00:1c.0 mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
Unknown device path type: 0
14 * [0x0 - 0x7fffff] prefmem
PCI: 00:1c.3 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
Unknown device path type: 0
10 * [0x0 - 0x7fffff] mem
PCI: 03:00.3 10 * [0x800000 - 0x8007ff] mem
PCI: 03:00.0 10 * [0x801000 - 0x8010ff] mem
PCI: 03:00.1 10 * [0x802000 - 0x8020ff] mem
PCI: 03:00.2 10 * [0x803000 - 0x8030ff] mem
PCI: 00:1c.3 mem: base: 803100 size: 900000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
PCI: 00:1c.3 20 * [0x10000000 - 0x108fffff] mem
PCI: 00:1c.3 24 * [0x10c00000 - 0x113fffff] prefmem
PCI: 00:02.0 10 * [0x11400000 - 0x117fffff] mem
PCI: 00:1c.0 20 * [0x11800000 - 0x118fffff] mem
PCI: 00:19.0 10 * [0x11900000 - 0x1191ffff] mem
PCI: 00:04.0 10 * [0x11920000 - 0x11927fff] mem
PCI: 00:1b.0 10 * [0x11928000 - 0x1192bfff] mem
PCI: 00:19.0 14 * [0x1192c000 - 0x1192cfff] mem
PCI: 00:1f.6 10 * [0x1192d000 - 0x1192dfff] mem
PCI: 00:1f.2 24 * [0x1192e000 - 0x1192e7ff] mem
PCI: 00:1a.0 10 * [0x1192f000 - 0x1192f3ff] mem
PCI: 00:1d.0 10 * [0x11930000 - 0x119303ff] mem
PCI: 00:1f.3 10 * [0x11931000 - 0x119310ff] mem
PCI: 00:16.0 10 * [0x11932000 - 0x1193200f] mem
DOMAIN: 0000 mem: base: 11932010 size: 11932010 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 cf base f8000000 limit fbffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
skipping PNP: 00ff.2 at 60 fixed resource, size=0!
skipping PNP: 00ff.2 at 62 fixed resource, size=0!
skipping PNP: 00ff.2 at 64 fixed resource, size=0!
skipping PNP: 00ff.2 at 66 fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff
Setting resources...
DOMAIN: 0000 io: base:167c size:1098 align:12 gran:0 limit:ffff
PCI: 00:1c.3 1c * [0x2000 - 0x2fff] io
PCI: 00:02.0 20 * [0x3000 - 0x303f] io
PCI: 00:19.0 18 * [0x3040 - 0x305f] io
PCI: 00:1f.2 20 * [0x3060 - 0x307f] io
PCI: 00:1f.2 10 * [0x3080 - 0x3087] io
PCI: 00:1f.2 18 * [0x3088 - 0x308f] io
PCI: 00:1f.2 14 * [0x3090 - 0x3093] io
PCI: 00:1f.2 1c * [0x3094 - 0x3097] io
DOMAIN: 0000 io: next_base: 3098 size: 1098 align: 12 gran: 0 done
PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.2 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.2 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.3 io: base:2000 size:1000 align:12 gran:12 limit:2fff
Unknown device path type: 0
18 * [0x2000 - 0x2fff] io
PCI: 00:1c.3 io: next_base: 3000 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e0000000 size:11932010 align:28 gran:0 limit:f7ffffff
PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem
PCI: 00:1c.3 20 * [0xf0000000 - 0xf08fffff] mem
PCI: 00:1c.3 24 * [0xf0c00000 - 0xf13fffff] prefmem
PCI: 00:02.0 10 * [0xf1400000 - 0xf17fffff] mem
PCI: 00:1c.0 20 * [0xf1800000 - 0xf18fffff] mem
PCI: 00:19.0 10 * [0xf1900000 - 0xf191ffff] mem
PCI: 00:04.0 10 * [0xf1920000 - 0xf1927fff] mem
PCI: 00:1b.0 10 * [0xf1928000 - 0xf192bfff] mem
PCI: 00:19.0 14 * [0xf192c000 - 0xf192cfff] mem
PCI: 00:1f.6 10 * [0xf192d000 - 0xf192dfff] mem
PCI: 00:1f.2 24 * [0xf192e000 - 0xf192e7ff] mem
PCI: 00:1a.0 10 * [0xf192f000 - 0xf192f3ff] mem
PCI: 00:1d.0 10 * [0xf1930000 - 0xf19303ff] mem
PCI: 00:1f.3 10 * [0xf1931000 - 0xf19310ff] mem
PCI: 00:16.0 10 * [0xf1932000 - 0xf193200f] mem
DOMAIN: 0000 mem: next_base: f1932010 size: 11932010 align: 28 gran: 0 done
PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 mem: base:f1800000 size:100000 align:20 gran:20 limit:f18fffff
PCI: 01:00.0 10 * [0xf1800000 - 0xf181ffff] mem
PCI: 01:00.0 30 * [0xf1820000 - 0xf182ffff] mem
PCI: 00:1c.0 mem: next_base: f1830000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.2 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.2 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 prefmem: base:f0c00000 size:800000 align:22 gran:20 limit:f13fffff
Unknown device path type: 0
14 * [0xf0c00000 - 0xf13fffff] prefmem
PCI: 00:1c.3 prefmem: next_base: f1400000 size: 800000 align: 22 gran: 20 done
PCI: 00:1c.3 mem: base:f0000000 size:900000 align:22 gran:20 limit:f08fffff
Unknown device path type: 0
10 * [0xf0000000 - 0xf07fffff] mem
PCI: 03:00.3 10 * [0xf0800000 - 0xf08007ff] mem
PCI: 03:00.0 10 * [0xf0801000 - 0xf08010ff] mem
PCI: 03:00.1 10 * [0xf0802000 - 0xf08020ff] mem
PCI: 03:00.2 10 * [0xf0803000 - 0xf08030ff] mem
PCI: 00:1c.3 mem: next_base: f0803100 size: 900000 align: 22 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x27ce00000 TOLUD 0x82a00000 TOM 0x200000000
MEBASE 0x1ff800000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0x80000000 size 8M
Available memory below 4GB: 2048M
Available memory above 4GB: 6094M
Adding PCIe config bar base=0xf8000000 size=0x4000000
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:02.0 10 <- [0x00f1400000 - 0x00f17fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x00f1920000 - 0x00f1927fff] size 0x00008000 gran 0x0f mem64
PCI: 00:16.0 10 <- [0x00f1932000 - 0x00f193200f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00f1900000 - 0x00f191ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00f192c000 - 0x00f192cfff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 10 <- [0x00f192f000 - 0x00f192f3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00f1928000 - 0x00f192bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00f1800000 - 0x00f18fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f1800000 - 0x00f181ffff] size 0x00020000 gran 0x11 mem64
PCI: 01:00.0 30 <- [0x00f1820000 - 0x00f182ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.2 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:1c.3 24 <- [0x00f0c00000 - 0x00f13fffff] size 0x00800000 gran 0x14 bus 03 prefmem
PCI: 00:1c.3 20 <- [0x00f0000000 - 0x00f08fffff] size 0x00900000 gran 0x14 bus 03 mem
PCI: 00:1c.3 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00f0801000 - 0x00f08010ff] size 0x00000100 gran 0x08 mem
PCI: 03:00.1 10 <- [0x00f0802000 - 0x00f08020ff] size 0x00000100 gran 0x08 mem
PCI: 03:00.2 10 <- [0x00f0803000 - 0x00f08030ff] size 0x00000100 gran 0x08 mem
PCI: 03:00.3 10 <- [0x00f0800000 - 0x00f08007ff] size 0x00000800 gran 0x0b mem
Unknown device path type: 0
missing set_resources
PCI: 00:1c.3 assign_resources, bus 3 link: 0
PCI: 00:1d.0 EHCI Debug Port hook triggered
PCI: 00:1d.0 10 <- [0x00f1930000 - 0x00f19303ff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 10 <- [0x00f1930000 - 0x00f19303ff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 EHCI Debug Port relocated
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00f192e000 - 0x00f192e7ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00f1931000 - 0x00f19310ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.6 10 <- [0x00f192d000 - 0x00f192dfff] size 0x00001000 gran 0x0c mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: acac
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 167c size 1098 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base e0000000 size 11932010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4
DOMAIN: 0000 resource base 100000000 size 17ce00000 align 0 gran 0 limit 0 flags e0004200 index 5
DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
DOMAIN: 0000 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:01.0
PCI: 00:02.0
PCI: 00:02.0 resource base f1400000 size 400000 align 22 gran 22 limit f17fffff flags 60000201 index 10
PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20
PCI: 00:04.0
PCI: 00:04.0 resource base f1920000 size 8000 align 15 gran 15 limit f1927fff flags 60000201 index 10
PCI: 00:16.0
PCI: 00:16.0 resource base f1932000 size 10 align 12 gran 4 limit f193200f flags 60000201 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:19.0 resource base f1900000 size 20000 align 17 gran 17 limit f191ffff flags 60000200 index 10
PCI: 00:19.0 resource base f192c000 size 1000 align 12 gran 12 limit f192cfff flags 60000200 index 14
PCI: 00:19.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 18
PCI: 00:1a.0
PCI: 00:1a.0 resource base f192f000 size 400 align 12 gran 10 limit f192f3ff flags 60000200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base f1928000 size 4000 align 14 gran 14 limit f192bfff flags 60000201 index 10
PCI: 00:1c.7
PCI: 00:1c.0 child on link 0 PCI: 01:00.0
PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:1c.0 resource base f1800000 size 100000 align 20 gran 20 limit f18fffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base f1800000 size 20000 align 17 gran 17 limit f181ffff flags 60000201 index 10
PCI: 01:00.0 resource base f1820000 size 10000 align 16 gran 16 limit f182ffff flags 60002200 index 30
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 00:1c.3 child on link 0 PCI: 03:00.0
PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
PCI: 00:1c.3 resource base f0c00000 size 800000 align 22 gran 20 limit f13fffff flags 60081202 index 24
PCI: 00:1c.3 resource base f0000000 size 900000 align 22 gran 20 limit f08fffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base f0801000 size 100 align 12 gran 8 limit f08010ff flags 60000200 index 10
PCI: 03:00.1
PCI: 03:00.1 resource base f0802000 size 100 align 12 gran 8 limit f08020ff flags 60000200 index 10
PCI: 03:00.2
PCI: 03:00.2 resource base f0803000 size 100 align 12 gran 8 limit f08030ff flags 60000200 index 10
PCI: 03:00.3
PCI: 03:00.3 resource base f0800000 size 800 align 12 gran 11 limit f08007ff flags 60000200 index 10
Unknown device path type: 0
Unknown device path type: 0
resource base f0000000 size 800000 align 22 gran 22 limit f07fffff flags 40000200 index 10
Unknown device path type: 0
resource base f0c00000 size 800000 align 22 gran 22 limit f13fffff flags 40001200 index 14
Unknown device path type: 0
resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18
PCI: 00:1c.5
PCI: 00:1c.4
PCI: 00:1c.6
PCI: 00:1d.0
PCI: 00:1d.0 resource base f1930000 size 400 align 12 gran 10 limit f19303ff flags 60000200 index 10
PCI: 00:1f.0 child on link 0 PNP: 00ff.1
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
PNP: 00ff.1
PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
PNP: 0c31.0
PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
PNP: 00ff.2
PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
PCI: 00:1f.2
PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10
PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14
PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18
PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c
PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20
PCI: 00:1f.2 resource base f192e000 size 800 align 12 gran 11 limit f192e7ff flags 60000200 index 24
PCI: 00:1f.3 child on link 0 I2C: 01:54
PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
PCI: 00:1f.3 resource base f1931000 size 100 align 12 gran 8 limit f19310ff flags 60000201 index 10
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:5c
I2C: 01:5d
I2C: 01:5e
I2C: 01:5f
PCI: 00:1f.6
PCI: 00:1f.6 resource base f192d000 size 1000 align 12 gran 12 limit f192dfff flags 60000201 index 10
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 13670 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 0000/0000
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 cmd <- 02
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 0000/0000
PCI: 00:19.0 cmd <- 103
PCI: 00:1a.0 subsystem <- 0000/0000
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 0000/0000
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 0000/0000
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.2 bridge ctrl <- 0003
PCI: 00:1c.2 subsystem <- 0000/0000
PCI: 00:1c.2 cmd <- 100
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 subsystem <- 0000/0000
PCI: 00:1c.3 cmd <- 107
PCI: 00:1d.0 subsystem <- 0000/0000
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 0000/0000
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 0000/0000
PCI: 00:1f.3 cmd <- 103
PCI: 00:1f.6 cmd <- 02
PCI: 01:00.0 cmd <- 02
PCI: 03:00.0 cmd <- 06
PCI: 03:00.1 cmd <- 06
PCI: 03:00.2 cmd <- 06
PCI: 03:00.3 cmd <- 02
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 602 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 9 usecs
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
Setting up SMI for CPU
Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x00038000
Adjusting 00038002: 0x00000024 -> 0x00038024
Adjusting 0003801d: 0x0000003c -> 0x0003803c
Adjusting 00038026: 0x00000024 -> 0x00038024
Adjusting 00038054: 0x000000d8 -> 0x000380d8
Adjusting 00038066: 0x00000160 -> 0x00038160
Adjusting 0003806d: 0x000000c0 -> 0x000380c0
Adjusting 00038075: 0x000000c4 -> 0x000380c4
Adjusting 0003807e: 0x000000d0 -> 0x000380d0
Adjusting 00038085: 0x000000cc -> 0x000380cc
Adjusting 0003808b: 0x000000c8 -> 0x000380c8
SMM Module: stub loaded at 00038000. Will call 00115f26(00135900)
Installing SMM handler to 0x80000000
Loading module at 80010000 with entry 8001056d. filesize: 0x18d8 memsize: 0x58f8
Processing 75 relocs. Offset value of 0x80010000
Adjusting 80010036: 0x000017dc -> 0x800117dc
Adjusting 80010055: 0x000017dc -> 0x800117dc
Adjusting 80010108: 0x000017dc -> 0x800117dc
Adjusting 80010198: 0x00001736 -> 0x80011736
Adjusting 800104bc: 0x000018d8 -> 0x800118d8
Adjusting 800104d6: 0x000018e0 -> 0x800118e0
Adjusting 800104ed: 0x000018e0 -> 0x800118e0
Adjusting 8001053a: 0x000018d0 -> 0x800118d0
Adjusting 80010550: 0x00001820 -> 0x80011820
Adjusting 80010576: 0x000018d8 -> 0x800118d8
Adjusting 80010584: 0x000018d8 -> 0x800118d8
Adjusting 80010591: 0x000018c0 -> 0x800118c0
Adjusting 8001059c: 0x000018c0 -> 0x800118c0
Adjusting 800105b0: 0x000018c4 -> 0x800118c4
Adjusting 800105b6: 0x000018dc -> 0x800118dc
Adjusting 800105be: 0x000018c4 -> 0x800118c4
Adjusting 800105db: 0x000018dc -> 0x800118dc
Adjusting 800105e4: 0x000018c0 -> 0x800118c0
Adjusting 80010700: 0x0000173f -> 0x8001173f
Adjusting 8001080e: 0x000018cc -> 0x800118cc
Adjusting 80010837: 0x000018cc -> 0x800118cc
Adjusting 80010854: 0x000018cc -> 0x800118cc
Adjusting 8001087d: 0x000018c8 -> 0x800118c8
Adjusting 8001089a: 0x000018cc -> 0x800118cc
Adjusting 800108c0: 0x000018c8 -> 0x800118c8
Adjusting 80010978: 0x000018cc -> 0x800118cc
Adjusting 8001097d: 0x000018c8 -> 0x800118c8
Adjusting 8001098c: 0x000017c8 -> 0x800117c8
Adjusting 80010ca3: 0x000018e4 -> 0x800118e4
Adjusting 80010cd2: 0x000018e8 -> 0x800118e8
Adjusting 80010ce5: 0x000018e4 -> 0x800118e4
Adjusting 80010d08: 0x000018e8 -> 0x800118e8
Adjusting 80010dcb: 0x000018e4 -> 0x800118e4
Adjusting 80011006: 0x000018e8 -> 0x800118e8
Adjusting 800111f5: 0x000018e8 -> 0x800118e8
Adjusting 800112d7: 0x000018d0 -> 0x800118d0
Adjusting 800112e7: 0x000018d0 -> 0x800118d0
Adjusting 800112fc: 0x000018d0 -> 0x800118d0
Adjusting 8001131d: 0x000018d0 -> 0x800118d0
Adjusting 8001134c: 0x000018d0 -> 0x800118d0
Adjusting 8001136b: 0x000018d0 -> 0x800118d0
Adjusting 8001137e: 0x000018f4 -> 0x800118f4
Adjusting 800113c2: 0x000018ec -> 0x800118ec
Adjusting 800113df: 0x000018ec -> 0x800118ec
Adjusting 800113fd: 0x000018f4 -> 0x800118f4
Adjusting 80011403: 0x000018f0 -> 0x800118f0
Adjusting 80011410: 0x000018d0 -> 0x800118d0
Adjusting 80011436: 0x000018d0 -> 0x800118d0
Adjusting 8001148b: 0x000018f0 -> 0x800118f0
Adjusting 800114e2: 0x000017ab -> 0x800117ab
Adjusting 800114fd: 0x000018d0 -> 0x800118d0
Adjusting 8001151e: 0x00001800 -> 0x80011800
Adjusting 80011523: 0x000018f0 -> 0x800118f0
Adjusting 800115e6: 0x000018d0 -> 0x800118d0
Adjusting 80011614: 0x000018d0 -> 0x800118d0
Adjusting 8001165d: 0x000018d0 -> 0x800118d0
Adjusting 800116fb: 0x000018f0 -> 0x800118f0
Adjusting 8001170f: 0x000018d0 -> 0x800118d0
Adjusting 800117c0: 0x00001720 -> 0x80011720
Adjusting 800117c8: 0x00000021 -> 0x80010021
Adjusting 800117cc: 0x00001720 -> 0x80011720
Adjusting 800117d4: 0x00000092 -> 0x80010092
Adjusting 800117e0: 0x000017ec -> 0x800117ec
Adjusting 800117ec: 0x000002d2 -> 0x800102d2
Adjusting 800117f0: 0x000002de -> 0x800102de
Adjusting 800117f4: 0x000002e1 -> 0x800102e1
Adjusting 80011830: 0x000014cc -> 0x800114cc
Adjusting 80011834: 0x0000132d -> 0x8001132d
Adjusting 80011840: 0x0000140d -> 0x8001140d
Adjusting 80011844: 0x000012d4 -> 0x800112d4
Adjusting 80011848: 0x000012f5 -> 0x800112f5
Adjusting 8001184c: 0x000012f0 -> 0x800112f0
Adjusting 80011854: 0x00001433 -> 0x80011433
Adjusting 80011858: 0x000012e4 -> 0x800112e4
Adjusting 80011874: 0x00001476 -> 0x80011476
Loading module at 80008000 with entry 80008000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x80008000
Adjusting 80008002: 0x00000024 -> 0x80008024
Adjusting 8000801d: 0x0000003c -> 0x8000803c
Adjusting 80008026: 0x00000024 -> 0x80008024
Adjusting 80008054: 0x000000d8 -> 0x800080d8
Adjusting 80008066: 0x00000160 -> 0x80008160
Adjusting 8000806d: 0x000000c0 -> 0x800080c0
Adjusting 80008075: 0x000000c4 -> 0x800080c4
Adjusting 8000807e: 0x000000d0 -> 0x800080d0
Adjusting 80008085: 0x000000cc -> 0x800080cc
Adjusting 8000808b: 0x000000c8 -> 0x800080c8
SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 80007800 rel16 0x07fd
SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd
SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd
SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd
SMM Module: placing jmp sequence at 80006800 rel16 0x17fd
SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd
SMM Module: stub loaded at 80008000. Will call 8001056d(00000000)
Initializing southbridge SMI... ... pmbase = 0x0500
SMI_STS: MCSMI PM1
PM1_STS: WAK PWRBTN TMROF
GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI5 GPI4 GPI3 GPI1 GPI0
TCO_STS: INTRD_DET
... raise SMI#
In relocation handler: cpu 0
New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
Locking SMM.
Initializing CPU #0
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000e0000000 size 0x60000000 type 0
0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1
0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0
0x0000000100000000 - 0x000000027ce00000 size 0x17ce00000 type 6
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR addr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc1 set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd2-0xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTRR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type @ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 4/7.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0
MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x00 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
Turbo is available but hidden
Turbo has been enabled
CPU: 0 has 4 cores, 2 threads per core
CPU: 0 has core 1
CPU1: stack_base 0012f000, stack_end 0012fff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
In relocation handler: cpu 1
New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: 0 has core 2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x01 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #1 initialized
CPU2: stack_base 0012e000, stack_end 0012eff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
In relocation handler: cpu 2
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 2.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 3
Initializing CPU #2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x02 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #2 initialized
CPU3: stack_base 0012d000, stack_end 0012dff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
In relocation handler: cpu 3
New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 4
Initializing CPU #3
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x03 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #3 initialized
CPU4: stack_base 0012c000, stack_end 0012cff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 4.
After apic_write.
In relocation handler: cpu 4
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 4.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 5
Initializing CPU #4
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x04 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #4 initialized
CPU5: stack_base 0012b000, stack_end 0012bff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 5.
After apic_write.
In relocation handler: cpu 5
New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 5.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 6
Initializing CPU #5
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x05 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #5 initialized
CPU6: stack_base 0012a000, stack_end 0012aff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 6.
After apic_write.
In relocation handler: cpu 6
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 6.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 7
Initializing CPU #6
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x06 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #6 initialized
CPU7: stack_base 00129000, stack_end 00129ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 7.
After apic_write.
In relocation handler: cpu 7
New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 7.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU #0 initialized
Waiting for 1 CPUS to stop
Initializing CPU #7
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x07 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #7 initialized
All AP CPUs stopped (659 loops)
CPU0: stack: 00130000 - 00131000, lowest used address 00130aa0, stack used: 1376 bytes
CPU1: stack: 0012f000 - 00130000, lowest used address 0012fc64, stack used: 924 bytes
CPU2: stack: 0012e000 - 0012f000, lowest used address 0012ec64, stack used: 924 bytes
CPU3: stack: 0012d000 - 0012e000, lowest used address 0012dc64, stack used: 924 bytes
CPU4: stack: 0012c000 - 0012d000, lowest used address 0012cc64, stack used: 924 bytes
CPU5: stack: 0012b000 - 0012c000, lowest used address 0012bc64, stack used: 924 bytes
CPU6: stack: 0012a000 - 0012b000, lowest used address 0012ac64, stack used: 924 bytes
CPU7: stack: 00129000 - 0012a000, lowest used address 00129c64, stack used: 924 bytes
CPU_CLUSTER: 0 init finished in 189039 usecs
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling PEG10.
Disabling PEG60.
Disabling PEG IO clock.
Set BIOS_RESET_CPL
CPU TDP: 55 Watts
PCI: 00:00.0 init finished in 1017 usecs
PCI: 00:02.0 init ...
GT Power Management Init
IVB GT2 35W Power Meter Weights
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 146 usecs
PCI: 00:04.0 init ...
PCI: 00:04.0 init finished in 0 usecs
PCI: 00:16.0 init ...
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : YES
ME: Manufacturing Mode : YES
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : Host Communication
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : Host communication established
ME: BIOS path: Normal
ME: Extend SHA-256: 8e5a7f7302a670b1c63946e89940074b55750c18ff28106b53bc7440f89457e3
ME: Firmware Version 7.1.1214.80 (code) 7.1.1214.80 (recovery)
ME Capability: Full Network manageability : disabled
ME Capability: Regular Network manageability : disabled
ME Capability: Manageability : disabled
ME Capability: Small business technology : disabled
ME Capability: Level III manageability : enabled
ME Capability: IntelR Anti-Theft (AT) : enabled
ME Capability: IntelR Capability Licensing Service (CLS) : enabled
ME Capability: IntelR Power Sharing Technology (MPC) : enabled
ME Capability: ICC Over Clocking : enabled
ME Capability: Protected Audio Video Path (PAVP) : enabled
ME Capability: IPV6 : disabled
ME Capability: KVM Remote Control (KVM) : disabled
ME Capability: Outbreak Containment Heuristic (OCH) : disabled
ME Capability: Virtual LAN (VLAN) : enabled
ME Capability: TLS : disabled
ME Capability: Wireless LAN (WLAN) : disabled
PCI: 00:16.0 init finished in 6157 usecs
PCI: 00:19.0 init ...
PCI: 00:19.0 init finished in 0 usecs
PCI: 00:1a.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 13 usecs
PCI: 00:1b.0 init ...
Azalia: base = f1928000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862805
Azalia: No verb!
Azalia: Initializing codec #0
Azalia: codec viddid: 14f1506e
Azalia: verb_size: 52
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 4308 usecs
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 8 usecs
PCI: 00:1c.2 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.2 init finished in 8 usecs
PCI: 00:1c.3 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.3 init finished in 10 usecs
PCI: 00:1d.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 13 usecs
PCI: 00:1f.0 init ...
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
reg 0x0000: 0x02000000
reg 0x0001: 0x00170020
reg 0x0002: 0x00170020
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
Set power off after power failure.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
NMI sources enabled.
CougarPoint PM init
rtc_failed = 0x0
RTC Init
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 753 usecs
PCI: 00:1f.2 init ...
SATA: Initializing...
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
SATA: Controller in AHCI mode.
ABAR: f192e000
PCI: 00:1f.2 init finished in 281 usecs
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 7 usecs
PCI: 00:1f.6 init ...
PCI: 00:1f.6 init finished in 0 usecs
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 0 usecs
PCI: 03:00.0 init ...
PCI: 03:00.0 init finished in 0 usecs
PCI: 03:00.1 init ...
PCI: 03:00.1 init finished in 0 usecs
PCI: 03:00.2 init ...
PCI: 03:00.2 init finished in 0 usecs
PCI: 03:00.3 init ...
PCI: 03:00.3 init finished in 0 usecs
PNP: 00ff.2 init ...
PNP: 00ff.2 init finished in 0 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
I2C: 01:54 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
I2C: 01:55 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
I2C: 01:56 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
I2C: 01:57 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init finished in 26581 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
I2C: 01:5d init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
I2C: 01:5e init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
I2C: 01:5f init finished in 1 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 0
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.7: enabled 0
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.4: enabled 0
PCI: 00:1c.6: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:5c: enabled 1
I2C: 01:5d: enabled 1
I2C: 01:5e: enabled 1
I2C: 01:5f: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:1f.6: enabled 1
PCI: 01:00.0: enabled 1
PCI: 03:00.0: enabled 1
PCI: 03:00.1: enabled 1
PCI: 03:00.2: enabled 1
PCI: 03:00.3: enabled 1
Unknown device path type: 0
: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
APIC: 06: enabled 1
APIC: 07: enabled 1
BS: BS_DEV_INIT times (us): entry 6 run 228565 exit 0
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 4 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
Updating MRC cache data.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset 2fec0 size 10000
find_current_mrc_cache_local: No valid MRC cache found.
SF: Detected W25Q64 with sector size 0x1000, total 0x800000
Need to erase the MRC cache region of 65536 bytes at ff9b0000
SF: Successfully erased 65536 bytes @ 0x1b0000
Finally: write MRC cache update to flash at ff9b0000
Successfully wrote MRC cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'normal/dsdt.aml'
CBFS: Found @ offset 244c0 size 3617
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'normal/slic'
CBFS: 'normal/slic' not found.
ACPI: Writing ACPI tables at 7feb0000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * IGD OpRegion
GET_VBIOS: 76a2 906a 7d 93 6c
VBIOS not found.
ACPI: * FADT
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Found 1 CPU(s) with 8 core(s) each.
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TCPA
TCPA log created at 7fe9d000
ACPI: added table 4/32, length now 52
ACPI: * MADT
ACPI: added table 5/32, length now 56
current = 7feb6320
ACPI: * DMAR
ACPI: added table 6/32, length now 60
current = 7feb63d0
ACPI: * HPET
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 25616 bytes.
smbios_write_tables: 7fe9c000
recv_ec_data: 0x38
recv_ec_data: 0x41
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x38
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
Create SMBIOS type 17
Root Device (LENOVO ThinkPad W520)
CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
APIC: 00 (unknown)
APIC: acac (Intel SandyBridge/IvyBridge CPU)
DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
PNP: 0c31.0 (LPC TPM)
PNP: 00ff.2 (Lenovo H8 EC)
PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
I2C: 01:54 (AT24RF08C)
I2C: 01:55 (AT24RF08C)
I2C: 01:56 (AT24RF08C)
I2C: 01:57 (AT24RF08C)
I2C: 01:5c (AT24RF08C)
I2C: 01:5d (AT24RF08C)
I2C: 01:5e (AT24RF08C)
I2C: 01:5f (AT24RF08C)
PCI: 00:04.0 (unknown)
PCI: 00:1f.6 (unknown)
PCI: 01:00.0 (unknown)
PCI: 03:00.0 (unknown)
PCI: 03:00.1 (unknown)
PCI: 03:00.2 (unknown)
PCI: 03:00.3 (unknown)
Unknown device path type: 0
(unknown)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
APIC: 06 (unknown)
APIC: 07 (unknown)
SMBIOS tables: 523 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3ff1
Writing coreboot table at 0x7fed4000
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fe9bfff: RAM
4. 000000007fe9c000-000000007fffffff: CONFIGURATION TABLES
5. 0000000080000000-00000000829fffff: RESERVED
6. 00000000f8000000-00000000fbffffff: RESERVED
7. 00000000fed40000-00000000fed44fff: RESERVED
8. 00000000fed90000-00000000fed91fff: RESERVED
9. 0000000100000000-000000027cdfffff: RAM
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
FMAP: Found "FLASH" version 1.1 at 180000.
FMAP: base = ff800000 size = 800000 #areas = 3
Wrote coreboot table at: 7fed4000, 0xb74 bytes, checksum 87f9
coreboot table: 2956 bytes.
IMD ROOT 0. 7ffff000 00001000
IMD SMALL 1. 7fffe000 00001000
CONSOLE 2. 7ffde000 00020000
TIME STAMP 3. 7ffdd000 00000400
MRC DATA 4. 7ffdc000 000005b0
ACPI RESUME 5. 7fedc000 00100000
COREBOOT 6. 7fed4000 00008000
ACPI 7. 7feb0000 00024000
ACPI GNVS 8. 7feaf000 00001000
4f444749 9. 7fead000 00002000
TCPA LOG 10. 7fe9d000 00010000
SMBIOS 11. 7fe9c000 00000800
IMD small region:
IMD ROOT 0. 7fffec00 00000400
CAR GLOBALS 1. 7fffea40 000001c0
USBDEBUG 2. 7fffe9e0 00000058
MEM INFO 3. 7fffe880 00000141
ROMSTAGE 4. 7fffe860 00000004
GDT 5. 7fffe660 00000200
BS: BS_WRITE_TABLES times (us): entry 424813 run 25747 exit 0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'normal/payload'
CBFS: Found @ offset 1bf600 size 64c9f
Loading segment from ROM address 0xffb3f728
code (compression=1)
New segment dstaddr 0x8200 memsize 0x1b3e4 srcaddr 0xffb3f77c filesize 0x9743
Loading segment from ROM address 0xffb3f744
code (compression=1)
New segment dstaddr 0x100000 memsize 0x129a28 srcaddr 0xffb48ebf filesize 0x5b508
Loading segment from ROM address 0xffb3f760
Entry Point 0x00008200
Bounce Buffer at 7fd38000, 1455000 bytes
Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000001b3e4 filesz: 0x0000000000009743
lb: [0x0000000000100000, 0x0000000000139970)
Post relocation: addr: 0x0000000000008200 memsz: 0x000000000001b3e4 filesz: 0x0000000000009743
using LZMA
[ 0x00008200, 0001bbab, 0x000235e4) <- ffb3f77c
Clearing Segment: addr: 0x000000000001bbab memsz: 0x0000000000007a39
dest 00008200, end 000235e4, bouncebuffer 7fd38000
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000129a28 filesz: 0x000000000005b508
lb: [0x0000000000100000, 0x0000000000139970)
segment: [0x0000000000100000, 0x000000000015b508, 0x0000000000229a28)
bounce: [0x000000007fd38000, 0x000000007fd93508, 0x000000007fe61a28)
Post relocation: addr: 0x000000007fd38000 memsz: 0x0000000000129a28 filesz: 0x000000000005b508
using LZMA
[ 0x7fd38000, 7fe61a28, 0x7fe61a28) <- ffb48ebf
dest 7fd38000, end 7fe61a28, bouncebuffer 7fd38000
move suffix around: from 7fd71970, to 139970, amount: f00b8
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 118917 exit 0
PCH watchdog disabled
Jumping to boot code at 00008200(7fed4000)
CPU0: stack: 00130000 - 00131000, lowest used address 00130aa0, stack used: 1376 bytes
entry = 0x00008200
lb_start = 0x00100000
lb_size = 0x00039970
buffer = 0x7fd38000
SeaBIOS (version rel-1.10.0-0-gd7adf60)
BUILD: gcc: (coreboot toolchain v1.43 August 31st, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
Found coreboot cbmem console @ 7ffde000
Found mainboard LENOVO ThinkPad W520
Relocating init from 0x000e4740 to 0x7fe4fe20 (size 49472)
Found CBFS header at 0xff980138
multiboot: eax=7fe46340, ebx=0
Found 20 PCI devices (max PCI bus is 03)
Copying SMBIOS entry point from 0x7fe9c000 to 0x000f0860
Copying ACPI RSDP from 0x7feb0000 to 0x000f0830
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.10.0-0-gd7adf60)
Machine UUID 56196001-5261-11cb-9404-b9288c86426a
EHCI init on dev 00:1a.0 (regs=0xf192f020)
EHCI init on dev 00:1d.0 (regs=0xf1930020)
AHCI controller at 00:1f.2, iobase 0xf192e000, irq 10
Searching bootorder for: /pci at i0cf8/*@1f,2/drive at 1/disk at 0
AHCI/1: Set transfer mode to UDMA-6
Searching bootorder for: /pci at i0cf8/pci-bridge at 1c,3/*@0
AHCI/1: registering: "AHCI/1: Samsung SSD 850 EVO 500GB ATA-9 Hard-Disk (440 GiBytes)"
Found 0 lpt ports
Found 0 serial ports
Searching bootorder for: /rom at img/smcoreinfo
Searching bootorder for: /rom at img/memtest
Searching bootorder for: /rom at img/coreinfo
Initialized USB HUB (0 ports used)
Initialized USB HUB (0 ports used)
PS2 keyboard initialized
All threads complete.
Scan for option roms
Press ESC for boot menu.
Searching bootorder for: HALT
drive 0x000f07c0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=922748928
Space available for UMB: cf800-ee800, f0000-f07c0
Returned 253952 bytes of ZoneHigh
e820 map has 9 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007fe9a000 = 1 RAM
4: 000000007fe9a000 - 0000000082a00000 = 2 RESERVED
5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
8: 0000000100000000 - 000000027ce00000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
-------------- next part --------------
coreboot-4.5-103-g25445dc-charlotte1 Mon Oct 31 19:29:56 UTC 2016 romstage starting...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
Back from sandybridge_early_initialization()
SMBus controller enabled.
CPU id(306a9): Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz
AES supported, TXT supported, VT supported
PCH type: QM67, device id: 1c4f, rev id 5
Intel ME early init
Intel ME firmware is ready
ME: Requested 8MB UMA
Starting native Platform init
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset 2fec0 size 10000
find_current_mrc_cache_local: picked entry 1 from cache block
Trying stored timings.
Starting RAM training (1).
PLL busy... PLL busy...done
MCU frequency is set at : 666 MHz
XOVER CLK [c14] = f000000
XOVER CMD [320c] = 4024000
XOVER CLK [d14] = 0
XOVER CMD [330c] = 4000
DBP [4000] = 146777
RAP [4004] = ca156465
OTHP [400c] = a0690
ODT stretch [400c] = 0
REFI [4298] = 5aae1450
SRFTP [42a4] = 41f97200
DBP [4400] = 146777
RAP [4404] = ca156465
OTHP [440c] = a0690
ODT stretch [440c] = 0
ODT stretch [440c] = a0690
REFI [4698] = 5aae1450
SRFTP [46a4] = 41f97200
Done dimm mapping
Update PCI-E configuration space:
PCI(0, 0, 0)[a0] = 0
PCI(0, 0, 0)[a4] = 4
PCI(0, 0, 0)[bc] = 82a00000
PCI(0, 0, 0)[a8] = 7ce00000
PCI(0, 0, 0)[ac] = 4
PCI(0, 0, 0)[b8] = 80000000
PCI(0, 0, 0)[b0] = 80a00000
PCI(0, 0, 0)[b4] = 80800000
PCI(0, 0, 0)[7c] = 7f
PCI(0, 0, 0)[70] = ff800000
PCI(0, 0, 0)[74] = 3
PCI(0, 0, 0)[78] = ff800c00
Done memory map
RCOMP...done
COMP2 done
COMP1 done
FORCE RCOMP and wait 20us...done
Done io registers
CPE
CP5b
CP5c
t123: 1912, 6000, 7620
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : BUP Phase
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : 0x4e
ME: FWS2: 0x164e0002
ME: Bist in progress: 0x0
ME: ICC Status : 0x1
ME: Invoke MEBx : 0x0
ME: CPU replaced : 0x0
ME: MBP ready : 0x0
ME: MFS failure : 0x0
ME: Warm reset req : 0x0
ME: CPU repl valid : 0x0
ME: (Reserved) : 0x0
ME: FW update req : 0x0
ME: (Reserved) : 0x0
ME: Current state : 0x4e
ME: Current PM event: 0x6
ME: Progress code : 0x1
Waited long enough, or CPU was not replaced, continue...
PASSED! Tell ME that DRAM is ready
ME: FWS2: 0x16500002
ME: Bist in progress: 0x0
ME: ICC Status : 0x1
ME: Invoke MEBx : 0x0
ME: CPU replaced : 0x0
ME: MBP ready
*** Log truncated, 1295 characters dropped. ***
CBMEM entry for DIMM info: 0x7fffe880
TPM initialization.
TPM: Init
Found TPM ST33ZP24 by ST Microelectronics
TPM: Open
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: OK.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 3ff00 size 12af1
Capability: type 0x01 @ 0x50
Capability: type 0x0a @ 0x58
coreboot-4.5-103-g25445dc-charlotte1 Mon Oct 31 19:29:56 UTC 2016 ramstage starting...
Moving GDT to 7fffe660...ok
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 1
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 1
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0154] ops
Normal boot.
PCI: 00:00.0 [8086/0154] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0151] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0166] enabled
PCI: 00:04.0 [8086/0153] enabled
PCI: 00:16.0 [8086/1c3a] ops
PCI: 00:16.0 [8086/1c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.2 [8086/1c3c] disabled No operations
PCI: 00:16.3: Disabling device
PCI: 00:16.3 [8086/1c3d] disabled No operations
PCI: 00:19.0 [8086/1502] enabled
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1c2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1c20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0: Disabling device
PCI: 00:1c.0: check set enabled
PCH: Remap PCIe function 1 to 0
PCI: 00:1c.1 [8086/0000] bus ops
PCI: 00:1c.1 [8086/1c12] enabled
PCH: Remap PCIe function 2 to 0
PCI: Static device PCI: 00:1c.2 not found, disabling it.
PCH: Remap PCIe function 3 to 0
PCI: 00:1c.3 [8086/0000] bus ops
PCI: 00:1c.3 [8086/1c16] enabled
PCH: Remap PCIe function 4 to 0
PCI: 00:1c.4 [8086/0000] bus ops
PCI: 00:1c.4 [8086/1c18] enabled
PCI: 00:1c.5: Disabling device
PCH: Remap PCIe function 6 to 0
PCI: Static device PCI: 00:1c.6 not found, disabling it.
PCI: 00:1c.7: Disabling device
PCH: RPFN 0x76543210 -> 0xf4d3210e
PCH: PCIe map 1c.0 -> 1c.6
PCH: PCIe map 1c.1 -> 1c.0
PCH: PCIe map 1c.2 -> 1c.1
PCH: PCIe map 1c.3 -> 1c.2
PCH: PCIe map 1c.4 -> 1c.3
PCH: PCIe map 1c.6 -> 1c.4
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1c26] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1c4f] enabled
PCI: 00:1f.2 [8086/0000] ops
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
PCI: 00:1f.2 [8086/1c01] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1c22] enabled
PCI: 00:1f.6 [8086/1c24] enabled
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [10de/0dfa] enabled
PCI: 01:00.1 [10de/0bea] enabled
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:01.0 took 644 usecs
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [168c/0030] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpointASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.0 took 339 usecs
PCI: 00:1c.2 scanning...
do_pci_scan_bridge for PCI: 00:1c.2
PCI: pci_scan_bus for bus 03
scan_bus: scanning of bus PCI: 00:1c.2 took 83 usecs
PCI: 00:1c.3 scanning...
do_pci_scan_bridge for PCI: 00:1c.3
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [1180/e823] enabled
PCI: 04:00.1 [1180/e232] enabled
PCI: 04:00.2 [1180/e852] enabled
PCI: 04:00.3 [1180/e832] enabled
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.3 took 1169 usecs
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
PNP: 00ff.1 enabled
PNP: 0c31.0 enabled
recv_ec_data: 0x38
recv_ec_data: 0x41
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x38
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
recv_ec_data: 0x00
recv_ec_data: 0x12
EC Firmware ID 8AHT38WW-3.20, Version 0.01C
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
recv_ec_data: 0x00
recv_ec_data: 0x10
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
recv_ec_data: 0x20
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
recv_ec_data: 0x30
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
recv_ec_data: 0x00
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
recv_ec_data: 0xa7
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
recv_ec_data: 0xc2
recv_ec_data: 0x70
PNP: 00ff.2 enabled
scan_lpc_bus for PCI: 00:1f.0 done
scan_bus: scanning of bus PCI: 00:1f.0 took 5974 usecs
PCI: 00:1f.3 scanning...
scan_smbus for PCI: 00:1f.3
smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_smbus for PCI: 00:1f.3 done
scan_bus: scanning of bus PCI: 00:1f.3 took 194 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 9811 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 9898 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 10810 exit 0
found VGA at PCI: 00:02.0
found VGA at PCI: 01:00.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
More than one caller of pci_ehci_read_resources from PCI: 00:1a.0
PCI: 00:1c.0 read_resources bus 2 link: 0
PCI: 00:1c.0 read_resources bus 2 link: 0 done
PCI: 00:1c.2 read_resources bus 3 link: 0
PCI: 00:1c.2 read_resources bus 3 link: 0 done
PCI: 00:1c.3 read_resources bus 4 link: 0
PCI: 00:1c.3 read_resources bus 4 link: 0 done
PCI: 00:1d.0 EHCI BAR hook registered
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI: 00:1f.3 read_resources bus 1 link: 0
PCI: 00:1f.3 read_resources bus 1 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: acac
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:01.0 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14
PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c
PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
PCI: 01:00.1
PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
PCI: 00:04.0
PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
PCI: 00:16.0
PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 00:1a.0
PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:1c.6
PCI: 00:1c.0 child on link 0 PCI: 02:00.0
PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 02:00.0
PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:1c.3 child on link 0 PCI: 04:00.0
PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 04:00.1
PCI: 04:00.1 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 04:00.2
PCI: 04:00.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 04:00.3
PCI: 04:00.3 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 10
Unknown device path type: 0
Unknown device path type: 0
resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10
Unknown device path type: 0
resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14
Unknown device path type: 0
resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18
PCI: 00:1c.5
PCI: 00:1c.4
PCI: 00:1c.7
PCI: 00:1d.0
PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1f.0 child on link 0 PNP: 00ff.1
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
PNP: 00ff.1
PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
PNP: 0c31.0
PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
PNP: 00ff.2
PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
PCI: 00:1f.2
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
PCI: 00:1f.3 child on link 0 I2C: 01:54
PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:5c
I2C: 01:5d
I2C: 01:5e
I2C: 01:5f
PCI: 00:1f.6
PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 24 * [0x0 - 0x7f] io
PCI: 00:01.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
Unknown device path type: 0
18 * [0x0 - 0xfff] io
PCI: 00:1c.3 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:1c.3 1c * [0x1000 - 0x1fff] io
PCI: 00:02.0 20 * [0x2000 - 0x203f] io
PCI: 00:19.0 18 * [0x2040 - 0x205f] io
PCI: 00:1f.2 20 * [0x2060 - 0x207f] io
PCI: 00:1f.2 10 * [0x2080 - 0x2087] io
PCI: 00:1f.2 18 * [0x2088 - 0x208f] io
PCI: 00:1f.2 14 * [0x2090 - 0x2093] io
PCI: 00:1f.2 1c * [0x2094 - 0x2097] io
DOMAIN: 0000 io: base: 2098 size: 2098 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 01:00.0 14 * [0x0 - 0xfffffff] prefmem
PCI: 01:00.0 1c * [0x10000000 - 0x11ffffff] prefmem
PCI: 00:01.0 prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0xffffff] mem
PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem
PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem
PCI: 00:01.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 02:00.0 30 * [0x20000 - 0x2ffff] mem
PCI: 00:1c.0 mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
Unknown device path type: 0
14 * [0x0 - 0x7fffff] prefmem
PCI: 00:1c.3 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
Unknown device path type: 0
10 * [0x0 - 0x7fffff] mem
PCI: 04:00.3 10 * [0x800000 - 0x8007ff] mem
PCI: 04:00.0 10 * [0x801000 - 0x8010ff] mem
PCI: 04:00.1 10 * [0x802000 - 0x8020ff] mem
PCI: 04:00.2 10 * [0x803000 - 0x8030ff] mem
PCI: 00:1c.3 mem: base: 803100 size: 900000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 * [0x0 - 0x11ffffff] prefmem
PCI: 00:02.0 18 * [0x20000000 - 0x2fffffff] prefmem
PCI: 00:01.0 20 * [0x30000000 - 0x310fffff] mem
PCI: 00:1c.3 20 * [0x31400000 - 0x31cfffff] mem
PCI: 00:1c.3 24 * [0x32000000 - 0x327fffff] prefmem
PCI: 00:02.0 10 * [0x32800000 - 0x32bfffff] mem
PCI: 00:1c.0 20 * [0x32c00000 - 0x32cfffff] mem
PCI: 00:19.0 10 * [0x32d00000 - 0x32d1ffff] mem
PCI: 00:04.0 10 * [0x32d20000 - 0x32d27fff] mem
PCI: 00:1b.0 10 * [0x32d28000 - 0x32d2bfff] mem
PCI: 00:19.0 14 * [0x32d2c000 - 0x32d2cfff] mem
PCI: 00:1f.6 10 * [0x32d2d000 - 0x32d2dfff] mem
PCI: 00:1f.2 24 * [0x32d2e000 - 0x32d2e7ff] mem
PCI: 00:1a.0 10 * [0x32d2f000 - 0x32d2f3ff] mem
PCI: 00:1d.0 10 * [0x32d30000 - 0x32d303ff] mem
PCI: 00:1f.3 10 * [0x32d31000 - 0x32d310ff] mem
PCI: 00:16.0 10 * [0x32d32000 - 0x32d3200f] mem
DOMAIN: 0000 mem: base: 32d32010 size: 32d32010 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 cf base f8000000 limit fbffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
skipping PNP: 00ff.2 at 60 fixed resource, size=0!
skipping PNP: 00ff.2 at 62 fixed resource, size=0!
skipping PNP: 00ff.2 at 64 fixed resource, size=0!
skipping PNP: 00ff.2 at 66 fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit f7ffffff
Setting resources...
DOMAIN: 0000 io: base:167c size:2098 align:12 gran:0 limit:ffff
PCI: 00:01.0 1c * [0x2000 - 0x2fff] io
PCI: 00:1c.3 1c * [0x3000 - 0x3fff] io
PCI: 00:02.0 20 * [0x4000 - 0x403f] io
PCI: 00:19.0 18 * [0x4040 - 0x405f] io
PCI: 00:1f.2 20 * [0x4060 - 0x407f] io
PCI: 00:1f.2 10 * [0x4080 - 0x4087] io
PCI: 00:1f.2 18 * [0x4088 - 0x408f] io
PCI: 00:1f.2 14 * [0x4090 - 0x4093] io
PCI: 00:1f.2 1c * [0x4094 - 0x4097] io
DOMAIN: 0000 io: next_base: 4098 size: 2098 align: 12 gran: 0 done
PCI: 00:01.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 01:00.0 24 * [0x2000 - 0x207f] io
PCI: 00:01.0 io: next_base: 2080 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.2 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.2 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.3 io: base:3000 size:1000 align:12 gran:12 limit:3fff
Unknown device path type: 0
18 * [0x3000 - 0x3fff] io
PCI: 00:1c.3 io: next_base: 4000 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:c0000000 size:32d32010 align:28 gran:0 limit:f7ffffff
PCI: 00:01.0 24 * [0xc0000000 - 0xd1ffffff] prefmem
PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem
PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem
PCI: 00:1c.3 20 * [0xf1400000 - 0xf1cfffff] mem
PCI: 00:1c.3 24 * [0xf2000000 - 0xf27fffff] prefmem
PCI: 00:02.0 10 * [0xf2800000 - 0xf2bfffff] mem
PCI: 00:1c.0 20 * [0xf2c00000 - 0xf2cfffff] mem
PCI: 00:19.0 10 * [0xf2d00000 - 0xf2d1ffff] mem
PCI: 00:04.0 10 * [0xf2d20000 - 0xf2d27fff] mem
PCI: 00:1b.0 10 * [0xf2d28000 - 0xf2d2bfff] mem
PCI: 00:19.0 14 * [0xf2d2c000 - 0xf2d2cfff] mem
PCI: 00:1f.6 10 * [0xf2d2d000 - 0xf2d2dfff] mem
PCI: 00:1f.2 24 * [0xf2d2e000 - 0xf2d2e7ff] mem
PCI: 00:1a.0 10 * [0xf2d2f000 - 0xf2d2f3ff] mem
PCI: 00:1d.0 10 * [0xf2d30000 - 0xf2d303ff] mem
PCI: 00:1f.3 10 * [0xf2d31000 - 0xf2d310ff] mem
PCI: 00:16.0 10 * [0xf2d32000 - 0xf2d3200f] mem
DOMAIN: 0000 mem: next_base: f2d32010 size: 32d32010 align: 28 gran: 0 done
PCI: 00:01.0 prefmem: base:c0000000 size:12000000 align:28 gran:20 limit:d1ffffff
PCI: 01:00.0 14 * [0xc0000000 - 0xcfffffff] prefmem
PCI: 01:00.0 1c * [0xd0000000 - 0xd1ffffff] prefmem
PCI: 00:01.0 prefmem: next_base: d2000000 size: 12000000 align: 28 gran: 20 done
PCI: 00:01.0 mem: base:f0000000 size:1100000 align:24 gran:20 limit:f10fffff
PCI: 01:00.0 10 * [0xf0000000 - 0xf0ffffff] mem
PCI: 01:00.0 30 * [0xf1000000 - 0xf107ffff] mem
PCI: 01:00.1 10 * [0xf1080000 - 0xf1083fff] mem
PCI: 00:01.0 mem: next_base: f1084000 size: 1100000 align: 24 gran: 20 done
PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 mem: base:f2c00000 size:100000 align:20 gran:20 limit:f2cfffff
PCI: 02:00.0 10 * [0xf2c00000 - 0xf2c1ffff] mem
PCI: 02:00.0 30 * [0xf2c20000 - 0xf2c2ffff] mem
PCI: 00:1c.0 mem: next_base: f2c30000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.2 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.2 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 prefmem: base:f2000000 size:800000 align:22 gran:20 limit:f27fffff
Unknown device path type: 0
14 * [0xf2000000 - 0xf27fffff] prefmem
PCI: 00:1c.3 prefmem: next_base: f2800000 size: 800000 align: 22 gran: 20 done
PCI: 00:1c.3 mem: base:f1400000 size:900000 align:22 gran:20 limit:f1cfffff
Unknown device path type: 0
10 * [0xf1400000 - 0xf1bfffff] mem
PCI: 04:00.3 10 * [0xf1c00000 - 0xf1c007ff] mem
PCI: 04:00.0 10 * [0xf1c01000 - 0xf1c010ff] mem
PCI: 04:00.1 10 * [0xf1c02000 - 0xf1c020ff] mem
PCI: 04:00.2 10 * [0xf1c03000 - 0xf1c030ff] mem
PCI: 00:1c.3 mem: next_base: f1c03100 size: 900000 align: 22 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x47ce00000 TOLUD 0x82a00000 TOM 0x400000000
MEBASE 0x3ff800000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0x80000000 size 8M
Available memory below 4GB: 2048M
Available memory above 4GB: 14286M
Adding PCIe config bar base=0xf8000000 size=0x4000000
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:01.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00d1ffffff] size 0x12000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem
PCI: 01:00.0 14 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 01:00.0 1c <- [0x00d0000000 - 0x00d1ffffff] size 0x02000000 gran 0x19 prefmem64
PCI: 01:00.0 24 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io
PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f107ffff] size 0x00080000 gran 0x13 romem
PCI: 01:00.1 10 <- [0x00f1080000 - 0x00f1083fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:02.0 10 <- [0x00f2800000 - 0x00f2bfffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000004000 - 0x000000403f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x00f2d20000 - 0x00f2d27fff] size 0x00008000 gran 0x0f mem64
PCI: 00:16.0 10 <- [0x00f2d32000 - 0x00f2d3200f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00f2d00000 - 0x00f2d1ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00f2d2c000 - 0x00f2d2cfff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000004040 - 0x000000405f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 10 <- [0x00f2d2f000 - 0x00f2d2f3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00f2d28000 - 0x00f2d2bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00f2c00000 - 0x00f2cfffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:1c.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00f2c00000 - 0x00f2c1ffff] size 0x00020000 gran 0x11 mem64
PCI: 02:00.0 30 <- [0x00f2c20000 - 0x00f2c2ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.0 assign_resources, bus 2 link: 0
PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.2 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:1c.3 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:1c.3 24 <- [0x00f2000000 - 0x00f27fffff] size 0x00800000 gran 0x14 bus 04 prefmem
PCI: 00:1c.3 20 <- [0x00f1400000 - 0x00f1cfffff] size 0x00900000 gran 0x14 bus 04 mem
PCI: 00:1c.3 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00f1c01000 - 0x00f1c010ff] size 0x00000100 gran 0x08 mem
PCI: 04:00.1 10 <- [0x00f1c02000 - 0x00f1c020ff] size 0x00000100 gran 0x08 mem
PCI: 04:00.2 10 <- [0x00f1c03000 - 0x00f1c030ff] size 0x00000100 gran 0x08 mem
PCI: 04:00.3 10 <- [0x00f1c00000 - 0x00f1c007ff] size 0x00000800 gran 0x0b mem
Unknown device path type: 0
missing set_resources
PCI: 00:1c.3 assign_resources, bus 4 link: 0
PCI: 00:1d.0 EHCI Debug Port hook triggered
PCI: 00:1d.0 10 <- [0x00f2d30000 - 0x00f2d303ff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 10 <- [0x00f2d30000 - 0x00f2d303ff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 EHCI Debug Port relocated
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000004080 - 0x0000004087] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000004090 - 0x0000004093] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000004088 - 0x000000408f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000004094 - 0x0000004097] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000004060 - 0x000000407f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00f2d2e000 - 0x00f2d2e7ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00f2d31000 - 0x00f2d310ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.6 10 <- [0x00f2d2d000 - 0x00f2d2dfff] size 0x00001000 gran 0x0c mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: acac
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 167c size 2098 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base c0000000 size 32d32010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4
DOMAIN: 0000 resource base 100000000 size 37ce00000 align 0 gran 0 limit 0 flags e0004200 index 5
DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
DOMAIN: 0000 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:01.0 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
PCI: 00:01.0 resource base c0000000 size 12000000 align 28 gran 20 limit d1ffffff flags 60081202 index 24
PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit f10fffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit f0ffffff flags 60000200 index 10
PCI: 01:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 14
PCI: 01:00.0 resource base d0000000 size 2000000 align 25 gran 25 limit d1ffffff flags 60001201 index 1c
PCI: 01:00.0 resource base 2000 size 80 align 7 gran 7 limit 207f flags 60000100 index 24
PCI: 01:00.0 resource base f1000000 size 80000 align 19 gran 19 limit f107ffff flags 60002200 index 30
PCI: 01:00.1
PCI: 01:00.1 resource base f1080000 size 4000 align 14 gran 14 limit f1083fff flags 60000200 index 10
PCI: 00:02.0
PCI: 00:02.0 resource base f2800000 size 400000 align 22 gran 22 limit f2bfffff flags 60000201 index 10
PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
PCI: 00:02.0 resource base 4000 size 40 align 6 gran 6 limit 403f flags 60000100 index 20
PCI: 00:04.0
PCI: 00:04.0 resource base f2d20000 size 8000 align 15 gran 15 limit f2d27fff flags 60000201 index 10
PCI: 00:16.0
PCI: 00:16.0 resource base f2d32000 size 10 align 12 gran 4 limit f2d3200f flags 60000201 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:19.0 resource base f2d00000 size 20000 align 17 gran 17 limit f2d1ffff flags 60000200 index 10
PCI: 00:19.0 resource base f2d2c000 size 1000 align 12 gran 12 limit f2d2cfff flags 60000200 index 14
PCI: 00:19.0 resource base 4040 size 20 align 5 gran 5 limit 405f flags 60000100 index 18
PCI: 00:1a.0
PCI: 00:1a.0 resource base f2d2f000 size 400 align 12 gran 10 limit f2d2f3ff flags 60000200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base f2d28000 size 4000 align 14 gran 14 limit f2d2bfff flags 60000201 index 10
PCI: 00:1c.6
PCI: 00:1c.0 child on link 0 PCI: 02:00.0
PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:1c.0 resource base f2c00000 size 100000 align 20 gran 20 limit f2cfffff flags 60080202 index 20
PCI: 02:00.0
PCI: 02:00.0 resource base f2c00000 size 20000 align 17 gran 17 limit f2c1ffff flags 60000201 index 10
PCI: 02:00.0 resource base f2c20000 size 10000 align 16 gran 16 limit f2c2ffff flags 60002200 index 30
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 00:1c.3 child on link 0 PCI: 04:00.0
PCI: 00:1c.3 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
PCI: 00:1c.3 resource base f2000000 size 800000 align 22 gran 20 limit f27fffff flags 60081202 index 24
PCI: 00:1c.3 resource base f1400000 size 900000 align 22 gran 20 limit f1cfffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base f1c01000 size 100 align 12 gran 8 limit f1c010ff flags 60000200 index 10
PCI: 04:00.1
PCI: 04:00.1 resource base f1c02000 size 100 align 12 gran 8 limit f1c020ff flags 60000200 index 10
PCI: 04:00.2
PCI: 04:00.2 resource base f1c03000 size 100 align 12 gran 8 limit f1c030ff flags 60000200 index 10
PCI: 04:00.3
PCI: 04:00.3 resource base f1c00000 size 800 align 12 gran 11 limit f1c007ff flags 60000200 index 10
Unknown device path type: 0
Unknown device path type: 0
resource base f1400000 size 800000 align 22 gran 22 limit f1bfffff flags 40000200 index 10
Unknown device path type: 0
resource base f2000000 size 800000 align 22 gran 22 limit f27fffff flags 40001200 index 14
Unknown device path type: 0
resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 40000100 index 18
PCI: 00:1c.5
PCI: 00:1c.4
PCI: 00:1c.7
PCI: 00:1d.0
PCI: 00:1d.0 resource base f2d30000 size 400 align 12 gran 10 limit f2d303ff flags 60000200 index 10
PCI: 00:1f.0 child on link 0 PNP: 00ff.1
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
PNP: 00ff.1
PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
PNP: 0c31.0
PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
PNP: 00ff.2
PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
PCI: 00:1f.2
PCI: 00:1f.2 resource base 4080 size 8 align 3 gran 3 limit 4087 flags 60000100 index 10
PCI: 00:1f.2 resource base 4090 size 4 align 2 gran 2 limit 4093 flags 60000100 index 14
PCI: 00:1f.2 resource base 4088 size 8 align 3 gran 3 limit 408f flags 60000100 index 18
PCI: 00:1f.2 resource base 4094 size 4 align 2 gran 2 limit 4097 flags 60000100 index 1c
PCI: 00:1f.2 resource base 4060 size 20 align 5 gran 5 limit 407f flags 60000100 index 20
PCI: 00:1f.2 resource base f2d2e000 size 800 align 12 gran 11 limit f2d2e7ff flags 60000200 index 24
PCI: 00:1f.3 child on link 0 I2C: 01:54
PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
PCI: 00:1f.3 resource base f2d31000 size 100 align 12 gran 8 limit f2d310ff flags 60000201 index 10
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:5c
I2C: 01:5d
I2C: 01:5e
I2C: 01:5f
PCI: 00:1f.6
PCI: 00:1f.6 resource base f2d2d000 size 1000 align 12 gran 12 limit f2d2dfff flags 60000201 index 10
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 15323 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 07
PCI: 00:02.0 subsystem <- 0000/0000
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 cmd <- 02
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 0000/0000
PCI: 00:19.0 cmd <- 103
PCI: 00:1a.0 subsystem <- 0000/0000
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 0000/0000
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 0000/0000
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.2 bridge ctrl <- 0003
PCI: 00:1c.2 subsystem <- 0000/0000
PCI: 00:1c.2 cmd <- 100
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 subsystem <- 0000/0000
PCI: 00:1c.3 cmd <- 107
PCI: 00:1d.0 subsystem <- 0000/0000
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 0000/0000
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 0000/0000
PCI: 00:1f.3 cmd <- 103
PCI: 00:1f.6 cmd <- 02
PCI: 01:00.0 cmd <- 03
PCI: 01:00.1 cmd <- 02
PCI: 02:00.0 cmd <- 02
PCI: 04:00.0 cmd <- 06
PCI: 04:00.1 cmd <- 06
PCI: 04:00.2 cmd <- 06
PCI: 04:00.3 cmd <- 02
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 628 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 9 usecs
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
Setting up SMI for CPU
Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x00038000
Adjusting 00038002: 0x00000024 -> 0x00038024
Adjusting 0003801d: 0x0000003c -> 0x0003803c
Adjusting 00038026: 0x00000024 -> 0x00038024
Adjusting 00038054: 0x000000d8 -> 0x000380d8
Adjusting 00038066: 0x00000160 -> 0x00038160
Adjusting 0003806d: 0x000000c0 -> 0x000380c0
Adjusting 00038075: 0x000000c4 -> 0x000380c4
Adjusting 0003807e: 0x000000d0 -> 0x000380d0
Adjusting 00038085: 0x000000cc -> 0x000380cc
Adjusting 0003808b: 0x000000c8 -> 0x000380c8
SMM Module: stub loaded at 00038000. Will call 001161a3(00135900)
Installing SMM handler to 0x80000000
Loading module at 80010000 with entry 8001056d. filesize: 0x18d8 memsize: 0x58f8
Processing 75 relocs. Offset value of 0x80010000
Adjusting 80010036: 0x000017dc -> 0x800117dc
Adjusting 80010055: 0x000017dc -> 0x800117dc
Adjusting 80010108: 0x000017dc -> 0x800117dc
Adjusting 80010198: 0x00001736 -> 0x80011736
Adjusting 800104bc: 0x000018d8 -> 0x800118d8
Adjusting 800104d6: 0x000018e0 -> 0x800118e0
Adjusting 800104ed: 0x000018e0 -> 0x800118e0
Adjusting 8001053a: 0x000018d0 -> 0x800118d0
Adjusting 80010550: 0x00001820 -> 0x80011820
Adjusting 80010576: 0x000018d8 -> 0x800118d8
Adjusting 80010584: 0x000018d8 -> 0x800118d8
Adjusting 80010591: 0x000018c0 -> 0x800118c0
Adjusting 8001059c: 0x000018c0 -> 0x800118c0
Adjusting 800105b0: 0x000018c4 -> 0x800118c4
Adjusting 800105b6: 0x000018dc -> 0x800118dc
Adjusting 800105be: 0x000018c4 -> 0x800118c4
Adjusting 800105db: 0x000018dc -> 0x800118dc
Adjusting 800105e4: 0x000018c0 -> 0x800118c0
Adjusting 80010700: 0x0000173f -> 0x8001173f
Adjusting 8001080e: 0x000018cc -> 0x800118cc
Adjusting 80010837: 0x000018cc -> 0x800118cc
Adjusting 80010854: 0x000018cc -> 0x800118cc
Adjusting 8001087d: 0x000018c8 -> 0x800118c8
Adjusting 8001089a: 0x000018cc -> 0x800118cc
Adjusting 800108c0: 0x000018c8 -> 0x800118c8
Adjusting 80010978: 0x000018cc -> 0x800118cc
Adjusting 8001097d: 0x000018c8 -> 0x800118c8
Adjusting 8001098c: 0x000017c8 -> 0x800117c8
Adjusting 80010ca3: 0x000018e4 -> 0x800118e4
Adjusting 80010cd2: 0x000018e8 -> 0x800118e8
Adjusting 80010ce5: 0x000018e4 -> 0x800118e4
Adjusting 80010d08: 0x000018e8 -> 0x800118e8
Adjusting 80010dcb: 0x000018e4 -> 0x800118e4
Adjusting 80011006: 0x000018e8 -> 0x800118e8
Adjusting 800111f5: 0x000018e8 -> 0x800118e8
Adjusting 800112d7: 0x000018d0 -> 0x800118d0
Adjusting 800112e7: 0x000018d0 -> 0x800118d0
Adjusting 800112fc: 0x000018d0 -> 0x800118d0
Adjusting 8001131d: 0x000018d0 -> 0x800118d0
Adjusting 8001134c: 0x000018d0 -> 0x800118d0
Adjusting 8001136b: 0x000018d0 -> 0x800118d0
Adjusting 8001137e: 0x000018f4 -> 0x800118f4
Adjusting 800113c2: 0x000018ec -> 0x800118ec
Adjusting 800113df: 0x000018ec -> 0x800118ec
Adjusting 800113fd: 0x000018f4 -> 0x800118f4
Adjusting 80011403: 0x000018f0 -> 0x800118f0
Adjusting 80011410: 0x000018d0 -> 0x800118d0
Adjusting 80011436: 0x000018d0 -> 0x800118d0
Adjusting 8001148b: 0x000018f0 -> 0x800118f0
Adjusting 800114e2: 0x000017ab -> 0x800117ab
Adjusting 800114fd: 0x000018d0 -> 0x800118d0
Adjusting 8001151e: 0x00001800 -> 0x80011800
Adjusting 80011523: 0x000018f0 -> 0x800118f0
Adjusting 800115e6: 0x000018d0 -> 0x800118d0
Adjusting 80011614: 0x000018d0 -> 0x800118d0
Adjusting 8001165d: 0x000018d0 -> 0x800118d0
Adjusting 800116fb: 0x000018f0 -> 0x800118f0
Adjusting 8001170f: 0x000018d0 -> 0x800118d0
Adjusting 800117c0: 0x00001720 -> 0x80011720
Adjusting 800117c8: 0x00000021 -> 0x80010021
Adjusting 800117cc: 0x00001720 -> 0x80011720
Adjusting 800117d4: 0x00000092 -> 0x80010092
Adjusting 800117e0: 0x000017ec -> 0x800117ec
Adjusting 800117ec: 0x000002d2 -> 0x800102d2
Adjusting 800117f0: 0x000002de -> 0x800102de
Adjusting 800117f4: 0x000002e1 -> 0x800102e1
Adjusting 80011830: 0x000014cc -> 0x800114cc
Adjusting 80011834: 0x0000132d -> 0x8001132d
Adjusting 80011840: 0x0000140d -> 0x8001140d
Adjusting 80011844: 0x000012d4 -> 0x800112d4
Adjusting 80011848: 0x000012f5 -> 0x800112f5
Adjusting 8001184c: 0x000012f0 -> 0x800112f0
Adjusting 80011854: 0x00001433 -> 0x80011433
Adjusting 80011858: 0x000012e4 -> 0x800112e4
Adjusting 80011874: 0x00001476 -> 0x80011476
Loading module at 80008000 with entry 80008000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x80008000
Adjusting 80008002: 0x00000024 -> 0x80008024
Adjusting 8000801d: 0x0000003c -> 0x8000803c
Adjusting 80008026: 0x00000024 -> 0x80008024
Adjusting 80008054: 0x000000d8 -> 0x800080d8
Adjusting 80008066: 0x00000160 -> 0x80008160
Adjusting 8000806d: 0x000000c0 -> 0x800080c0
Adjusting 80008075: 0x000000c4 -> 0x800080c4
Adjusting 8000807e: 0x000000d0 -> 0x800080d0
Adjusting 80008085: 0x000000cc -> 0x800080cc
Adjusting 8000808b: 0x000000c8 -> 0x800080c8
SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 80007800 rel16 0x07fd
SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd
SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd
SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd
SMM Module: placing jmp sequence at 80006800 rel16 0x17fd
SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd
SMM Module: stub loaded at 80008000. Will call 8001056d(00000000)
Initializing southbridge SMI... ... pmbase = 0x0500
SMI_STS: MCSMI PM1
PM1_STS: WAK PRBTNOR PWRBTN TMROF
GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI5 GPI4 GPI3 GPI1 GPI0
TCO_STS:
... raise SMI#
In relocation handler: cpu 0
New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
Locking SMM.
Initializing CPU #0
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000c0000000 size 0x40000000 type 0
0x00000000c0000000 - 0x00000000d2000000 size 0x12000000 type 1
0x00000000d2000000 - 0x00000000e0000000 size 0x0e000000 type 0
0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1
0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0
0x0000000100000000 - 0x000000047ce00000 size 0x37ce00000 type 6
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR addr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc1 set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd2-0xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTRR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type @ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 8/10.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 1
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ffe000000 type 1
MTRR: 3 base 0x00000000d2000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d4000000 mask 0x0000000ffc000000 type 0
MTRR: 5 base 0x00000000d8000000 mask 0x0000000ff8000000 type 0
MTRR: 6 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
MTRR: 7 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x00 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
Turbo is available but hidden
Turbo has been enabled
CPU: 0 has 4 cores, 2 threads per core
CPU: 0 has core 1
CPU1: stack_base 0012f000, stack_end 0012fff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
In relocation handler: cpu 1
New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: 0 has core 2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x01 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #1 initialized
CPU2: stack_base 0012e000, stack_end 0012eff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
In relocation handler: cpu 2
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 2.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 3
Initializing CPU #2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x02 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #2 initialized
CPU3: stack_base 0012d000, stack_end 0012dff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
In relocation handler: cpu 3
New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 4
Initializing CPU #3
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x03 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #3 initialized
CPU4: stack_base 0012c000, stack_end 0012cff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 4.
After apic_write.
In relocation handler: cpu 4
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 4.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 5
Initializing CPU #4
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x04 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #4 initialized
CPU5: stack_base 0012b000, stack_end 0012bff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 5.
After apic_write.
In relocation handler: cpu 5
New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 5.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 6
Initializing CPU #5
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x05 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #5 initialized
CPU6: stack_base 0012a000, stack_end 0012aff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 6.
After apic_write.
In relocation handler: cpu 6
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 6.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 7
Initializing CPU #6
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x06 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #6 initialized
CPU7: stack_base 00129000, stack_end 00129ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 7.
After apic_write.
In relocation handler: cpu 7
New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 7.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU #0 initialized
Waiting for 1 CPUS to stop
Initializing CPU #7
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x07 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #7 initialized
All AP CPUs stopped (641 loops)
CPU0: stack: 00130000 - 00131000, lowest used address 00130aa0, stack used: 1376 bytes
CPU1: stack: 0012f000 - 00130000, lowest used address 0012fc64, stack used: 924 bytes
CPU2: stack: 0012e000 - 0012f000, lowest used address 0012ec64, stack used: 924 bytes
CPU3: stack: 0012d000 - 0012e000, lowest used address 0012dc64, stack used: 924 bytes
CPU4: stack: 0012c000 - 0012d000, lowest used address 0012cc64, stack used: 924 bytes
CPU5: stack: 0012b000 - 0012c000, lowest used address 0012bc64, stack used: 924 bytes
CPU6: stack: 0012a000 - 0012b000, lowest used address 0012ac64, stack used: 924 bytes
CPU7: stack: 00129000 - 0012a000, lowest used address 00129c64, stack used: 924 bytes
CPU_CLUSTER: 0 init finished in 182351 usecs
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling PEG60.
Set BIOS_RESET_CPL
CPU TDP: 55 Watts
PCI: 00:00.0 init finished in 1015 usecs
PCI: 00:02.0 init ...
GT Power Management Init
IVB GT2 35W Power Meter Weights
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 147 usecs
PCI: 00:04.0 init ...
PCI: 00:04.0 init finished in 0 usecs
PCI: 00:16.0 init ...
PCI READ [40] : 0x00000040
PCI READ [48] : 0x00000048
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : YES
ME: Manufacturing Mode : YES
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : Host Communication
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : Host communication established
ME: BIOS path: Normal
PCI READ [bc] : 0x000000bc
ME: Extend SHA-256: 8e5a7f7302a670b1c63946e89940074b55750c18ff28106b53bc7440f89457e3
READ [04] : cbd=128 cbrp=00 cbwp=00 ready=0 reset=0 ig=0 is=1 ie=0
WRITE [04] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=1 ie=0
READ [04] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
WRITE [00] : CB: 0x80040007
WRITE [00] : CB: 0x000002ff
READ [04] : cbd=128 cbrp=00 cbwp=02 ready=1 reset=0 ig=0 is=0 ie=0
WRITE [04] : cbd=128 cbrp=00 cbwp=02 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=00 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [08] : CB: 0x80140007
READ [08] : CB: 0x000082ff
READ [08] : CB: 0x00070001
READ [08] : CB: 0x005004be
READ [08] : CB: 0x00070001
READ [08] : CB: 0x005004be
READ [04] : cbd=128 cbrp=02 cbwp=02 ready=1 reset=0 ig=0 is=1 ie=0
WRITE [04] : cbd=128 cbrp=02 cbwp=02 ready=1 reset=0 ig=1 is=1 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
ME: Firmware Version 7.1.1214.80 (code) 7.1.1214.80 (recovery)
READ [04] : cbd=128 cbrp=02 cbwp=02 ready=1 reset=0 ig=0 is=0 ie=0
WRITE [00] : CB: 0x80080007
WRITE [00] : CB: 0x00000203
WRITE [00] : CB: 0x00000000
READ [04] : cbd=128 cbrp=02 cbwp=05 ready=1 reset=0 ig=0 is=0 ie=0
WRITE [04] : cbd=128 cbrp=02 cbwp=05 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=1 is=0 ie=0
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=06 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=10 ready=1 reset=0 ig=0 is=0 ie=1
READ [0c] : cbd=128 cbrp=06 cbwp=11 ready=1 reset=0 ig=1 is=0 ie=1
READ [08] : CB: 0x800d0007
READ [08] : CB: 0x00008203
READ [08] : CB: 0x00000000
READ [08] : CB: 0x101c7004
READ [08] : CB: 0x00000001
READ [04] : cbd=128 cbrp=05 cbwp=05 ready=1 reset=0 ig=0 is=1 ie=0
WRITE [04] : cbd=128 cbrp=05 cbwp=05 ready=1 reset=0 ig=1 is=1 ie=0
READ [0c] : cbd=128 cbrp=11 cbwp=11 ready=1 reset=0 ig=0 is=0 ie=1
ME Capability: Full Network manageability : disabled
ME Capability: Regular Network manageability : disabled
ME Capability: Manageability : disabled
ME Capability: Small business technology : disabled
ME Capability: Level III manageability : enabled
ME Capability: IntelR Anti-Theft (AT) : enabled
ME Capability: IntelR Capability Licensing Service (CLS) : enabled
ME Capability: IntelR Power Sharing Technology (MPC) : enabled
ME Capability: ICC Over Clocking : enabled
ME Capability: Protected Audio Video Path (PAVP) : enabled
ME Capability: IPV6 : disabled
ME Capability: KVM Remote Control (KVM) : disabled
ME Capability: Outbreak Containment Heuristic (OCH) : disabled
ME Capability: Virtual LAN (VLAN) : enabled
ME Capability: TLS : disabled
ME Capability: Wireless LAN (WLAN) : disabled
PCI: 00:16.0 init finished in 6935 usecs
PCI: 00:19.0 init ...
PCI: 00:19.0 init finished in 0 usecs
PCI: 00:1a.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 13 usecs
PCI: 00:1b.0 init ...
Azalia: base = f2d28000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862805
Azalia: No verb!
Azalia: Initializing codec #0
Azalia: codec viddid: 14f1506e
Azalia: verb_size: 52
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 4309 usecs
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 8 usecs
PCI: 00:1c.2 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.2 init finished in 8 usecs
PCI: 00:1c.3 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.3 init finished in 10 usecs
PCI: 00:1d.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 13 usecs
PCI: 00:1f.0 init ...
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
reg 0x0000: 0x02000000
reg 0x0001: 0x00170020
reg 0x0002: 0x00170020
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
Set power off after power failure.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
NMI sources enabled.
CougarPoint PM init
rtc_failed = 0x0
RTC Init
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 745 usecs
PCI: 00:1f.2 init ...
SATA: Initializing...
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
SATA: Controller in AHCI mode.
ABAR: f2d2e000
PCI: 00:1f.2 init finished in 274 usecs
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 6 usecs
PCI: 00:1f.6 init ...
PCI: 00:1f.6 init finished in 0 usecs
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 0 usecs
PCI: 01:00.1 init ...
PCI: 01:00.1 init finished in 0 usecs
PCI: 02:00.0 init ...
PCI: 02:00.0 init finished in 0 usecs
PCI: 04:00.0 init ...
PCI: 04:00.0 init finished in 0 usecs
PCI: 04:00.1 init ...
PCI: 04:00.1 init finished in 0 usecs
PCI: 04:00.2 init ...
PCI: 04:00.2 init finished in 0 usecs
PCI: 04:00.3 init ...
PCI: 04:00.3 init finished in 0 usecs
PNP: 00ff.2 init ...
PNP: 00ff.2 init finished in 0 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
I2C: 01:54 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
I2C: 01:55 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
I2C: 01:56 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
I2C: 01:57 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init finished in 26726 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
I2C: 01:5d init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
I2C: 01:5e init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
I2C: 01:5f init finished in 1 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.6: enabled 0
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.4: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:5c: enabled 1
I2C: 01:5d: enabled 1
I2C: 01:5e: enabled 1
I2C: 01:5f: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:1f.6: enabled 1
PCI: 01:00.0: enabled 1
PCI: 01:00.1: enabled 1
PCI: 02:00.0: enabled 1
PCI: 04:00.0: enabled 1
PCI: 04:00.1: enabled 1
PCI: 04:00.2: enabled 1
PCI: 04:00.3: enabled 1
Unknown device path type: 0
: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
APIC: 06: enabled 1
APIC: 07: enabled 1
BS: BS_DEV_INIT times (us): entry 6 run 222792 exit 0
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 4 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
Updating MRC cache data.
No MRC cache in cbmem. Can't update flash.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 6a40 size 3617
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7feb1000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * IGD OpRegion
GET_VBIOS: 220c 95b4 a6 47 c0
VBIOS not found.
ACPI: * FADT
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Found 1 CPU(s) with 8 core(s) each.
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TCPA
TCPA log created at 7fe9e000
ACPI: added table 4/32, length now 52
ACPI: * MADT
ACPI: added table 5/32, length now 56
current = 7feb7320
ACPI: * DMAR
ACPI: added table 6/32, length now 60
current = 7feb73d0
ACPI: * HPET
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 25616 bytes.
smbios_write_tables: 7fe9d000
recv_ec_data: 0x38
recv_ec_data: 0x41
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x38
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
Create SMBIOS type 17
Root Device (LENOVO ThinkPad W520)
CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
APIC: 00 (unknown)
APIC: acac (Intel SandyBridge/IvyBridge CPU)
DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
PNP: 0c31.0 (LPC TPM)
PNP: 00ff.2 (Lenovo H8 EC)
PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
I2C: 01:54 (AT24RF08C)
I2C: 01:55 (AT24RF08C)
I2C: 01:56 (AT24RF08C)
I2C: 01:57 (AT24RF08C)
I2C: 01:5c (AT24RF08C)
I2C: 01:5d (AT24RF08C)
I2C: 01:5e (AT24RF08C)
I2C: 01:5f (AT24RF08C)
PCI: 00:04.0 (unknown)
PCI: 00:1f.6 (unknown)
PCI: 01:00.0 (unknown)
PCI: 01:00.1 (unknown)
PCI: 02:00.0 (unknown)
PCI: 04:00.0 (unknown)
PCI: 04:00.1 (unknown)
PCI: 04:00.2 (unknown)
PCI: 04:00.3 (unknown)
Unknown device path type: 0
(unknown)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
APIC: 06 (unknown)
APIC: 07 (unknown)
SMBIOS tables: 618 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 2ff1
Writing coreboot table at 0x7fed5000
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 5cc0 size 810
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fe9cfff: RAM
4. 000000007fe9d000-000000007fffffff: CONFIGURATION TABLES
5. 0000000080000000-00000000829fffff: RESERVED
6. 00000000f8000000-00000000fbffffff: RESERVED
7. 00000000fed40000-00000000fed44fff: RESERVED
8. 00000000fed90000-00000000fed91fff: RESERVED
9. 0000000100000000-000000047cdfffff: RAM
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
FMAP: Found "FLASH" version 1.1 at 180000.
FMAP: base = ff800000 size = 800000 #areas = 3
Wrote coreboot table at: 7fed5000, 0xb5c bytes, checksum 9228
coreboot table: 2932 bytes.
IMD ROOT 0. 7ffff000 00001000
IMD SMALL 1. 7fffe000 00001000
CONSOLE 2. 7ffde000 00020000
TIME STAMP 3. 7ffdd000 00000400
ACPI RESUME 4. 7fedd000 00100000
COREBOOT 5. 7fed5000 00008000
ACPI 6. 7feb1000 00024000
ACPI GNVS 7. 7feb0000 00001000
4f444749 8. 7feae000 00002000
TCPA LOG 9. 7fe9e000 00010000
SMBIOS 10. 7fe9d000 00000800
IMD small region:
IMD ROOT 0. 7fffec00 00000400
CAR GLOBALS 1. 7fffea40 000001c0
USBDEBUG 2. 7fffe9e0 00000058
MEM INFO 3. 7fffe880 00000141
ROMSTAGE 4. 7fffe860 00000004
GDT 5. 7fffe660 00000200
BS: BS_WRITE_TABLES times (us): entry 1 run 26381 exit 0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 62ac0 size f65f
Loading segment from ROM address 0xff9e2bf8
code (compression=1)
New segment dstaddr 0xe31e0 memsize 0x1ce20 srcaddr 0xff9e2c30 filesize 0xf627
Loading segment from ROM address 0xff9e2c14
Entry Point 0x000ff06e
Payload being loaded at below 1MiB without region being marked as RAM usable.
Bounce Buffer at 7fe29000, 471776 bytes
Loading Segment: addr: 0x00000000000e31e0 memsz: 0x000000000001ce20 filesz: 0x000000000000f627
lb: [0x0000000000100000, 0x0000000000139970)
Post relocation: addr: 0x00000000000e31e0 memsz: 0x000000000001ce20 filesz: 0x000000000000f627
using LZMA
[ 0x000e31e0, 00100000, 0x00100000) <- ff9e2c30
dest 000e31e0, end 00100000, bouncebuffer 7fe29000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 18416 exit 0
PCH watchdog disabled
Jumping to boot code at 000ff06e(7fed5000)
CPU0: stack: 00130000 - 00131000, lowest used address 00130aa0, stack used: 1376 bytes
entry = 0x000ff06e
lb_start = 0x00100000
lb_size = 0x00039970
buffer = 0x7fe29000
SeaBIOS (version rel-1.10.0-0-gd7adf60)
BUILD: gcc: (coreboot toolchain v1.43 August 31st, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
Found coreboot cbmem console @ 7ffde000
Found mainboard LENOVO ThinkPad W520
Relocating init from 0x000e4740 to 0x7fe50e20 (size 49472)
Found CBFS header at 0xff980138
multiboot: eax=0, ebx=0
Found 23 PCI devices (max PCI bus is 04)
Copying SMBIOS entry point from 0x7fe9d000 to 0x000f0860
Copying ACPI RSDP from 0x7feb1000 to 0x000f0830
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.10.0-0-gd7adf60)
Machine UUID 56196001-5261-11cb-9404-b9288c86426a
EHCI init on dev 00:1a.0 (regs=0xf2d2f020)
EHCI init on dev 00:1d.0 (regs=0xf2d30020)
AHCI controller at 00:1f.2, iobase 0xf2d2e000, irq 10
Searching bootorder for: /pci at i0cf8/pci-bridge at 1c,3/*@0
Found 0 lpt ports
Found 0 serial ports
Searching bootorder for: /rom at img/smcoreinfo
Searching bootorder for: /rom at img/memtest
Searching bootorder for: /rom at img/coreinfo
Discarding ps2 data aa (status=11)
Searching bootorder for: /pci at i0cf8/*@1f,2/drive at 1/disk at 0
AHCI/1: Set transfer mode to UDMA-6
AHCI/1: registering: "AHCI/1: Samsung SSD 850 EVO 500GB ATA-9 Hard-Disk (440 GiBytes)"
Initialized USB HUB (0 ports used)
Initialized USB HUB (0 ports used)
PS2 keyboard initialized
All threads complete.
Scan for option roms
Press ESC for boot menu.
Select boot device:
1. AHCI/1: Samsung SSD 850 EVO 500GB ATA-9 Hard-Disk (440 GiBy
2. Payload [smcoreinfo]
3. Payload [memtest]
4. Payload [coreinfo]
t. TPM Configuration
Searching bootorder for: HALT
drive 0x000f07c0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=922748928
Space available for UMB: cf800-ee800, f0000-f07c0
Returned 253952 bytes of ZoneHigh
e820 map has 9 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007fe9b000 = 1 RAM
4: 000000007fe9b000 - 0000000082a00000 = 2 RESERVED
5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
8: 0000000100000000 - 000000047ce00000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
-------------- next part --------------
coreboot-4.5-103-g25445dc-charlotte1 Mon Oct 31 19:29:56 UTC 2016 romstage starting...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
Back from sandybridge_early_initialization()
SMBus controller enabled.
CPU id(306a9): Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz
AES supported, TXT supported, VT supported
PCH type: QM67, device id: 1c4f, rev id 5
Intel ME early init
Intel ME firmware is ready
ME: Requested 8MB UMA
Starting native Platform init
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset 2fec0 size 10000
find_current_mrc_cache_local: No valid MRC cache found.
Revision : 11
Type : b
Key : 3
Banks : 8
Capacity : 4 Gb
Supported voltages : 1.35V 1.5V
SDRAM width : 8
Bus extension : 0 bits
Bus width : 64
Optional features : DLL-Off_mode RZQ/7 RZQ/6
Thermal features : PASR ext_temp_range
Thermal sensor : no
Standard SDRAM : yes
Rank1 Address bits : normal
DIMM Reference card: B
Manufacturer ID : 9e02
Part number : CMSX16GX3M2B2133
Revision : 11
Type : b
Key : 3
Banks : 8
Capacity : 4 Gb
Supported voltages : 1.35V 1.5V
SDRAM width : 8
Bus extension : 0 bits
Bus width : 64
Optional features : DLL-Off_mode RZQ/7 RZQ/6
Thermal features : PASR ext_temp_range
Thermal sensor : no
Standard SDRAM : yes
Rank1 Address bits : normal
DIMM Reference card: B
Manufacturer ID : 9e02
Part number : CMSX16GX3M2B2133
Revision : 11
Type : b
Key : 3
Banks : 8
Capacity : 4 Gb
Supported voltages : 1.35V 1.5V
SDRAM width : 8
Bus extension : 0 bits
Bus width : 64
Optional features : DLL-Off_mode RZQ/7 RZQ/6
Thermal features : PASR ext_temp_range
Thermal sensor : no
Standard SDRAM : yes
Rank1 Address bits : normal
DIMM Reference card: B
Manufacturer ID : 9e02
Part number : CMSX16GX3M2B2133
Not a DDR3 XMP profile!
No valid XMP profile found.
Revision : 11
Type : b
Key : 3
Banks : 8
Capacity : 4 Gb
Supported voltages : 1.35V 1.5V
SDRAM width : 8
Bus extension : 0 bits
Bus width : 64
Optional features : DLL-Off_mode RZQ/7 RZQ/6
Thermal features : PASR ext_temp_range
Thermal sensor : no
Standard SDRAM : yes
Rank1 Address bits : normal
DIMM Reference card: B
Manufacturer ID : 9e02
Part number : CMSX16GX3M2B2133
Row addr bi
*** Log truncated, 552148 characters dropped. ***
Relocate MRC DATA from fefff5e0 to 7ffdc000 (1440 bytes)
CBMEM entry for DIMM info: 0x7fffe880
TPM initialization.
TPM: Init
Found TPM ST33ZP24 by ST Microelectronics
TPM: Open
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: OK.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 3ff00 size 1297b
Capability: type 0x01 @ 0x50
Capability: type 0x0a @ 0x58
coreboot-4.5-103-g25445dc-charlotte1 Mon Oct 31 19:29:56 UTC 2016 ramstage starting...
Moving GDT to 7fffe660...ok
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 1
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 0
PCI: 00:1c.1: enabled 1
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 1
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 00:54: enabled 1
I2C: 00:55: enabled 1
I2C: 00:56: enabled 1
I2C: 00:57: enabled 1
I2C: 00:5c: enabled 1
I2C: 00:5d: enabled 1
I2C: 00:5e: enabled 1
I2C: 00:5f: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0154] ops
Normal boot.
PCI: 00:00.0 [8086/0154] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0151] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0166] enabled
PCI: 00:04.0 [8086/0153] enabled
PCI: 00:16.0 [8086/1c3a] ops
PCI: 00:16.0 [8086/1c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.2 [8086/1c3c] disabled No operations
PCI: 00:16.3: Disabling device
PCI: 00:16.3 [8086/1c3d] disabled No operations
PCI: 00:19.0 [8086/1502] enabled
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1c2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1c20] enabled
PCH: PCIe Root Port coalescing is enabled
PCI: 00:1c.0: Disabling device
PCI: 00:1c.0: check set enabled
PCH: Remap PCIe function 1 to 0
PCI: 00:1c.1 [8086/0000] bus ops
PCI: 00:1c.1 [8086/1c12] enabled
PCH: Remap PCIe function 2 to 0
PCI: Static device PCI: 00:1c.2 not found, disabling it.
PCH: Remap PCIe function 3 to 0
PCI: 00:1c.3 [8086/0000] bus ops
PCI: 00:1c.3 [8086/1c16] enabled
PCH: Remap PCIe function 4 to 0
PCI: 00:1c.4 [8086/0000] bus ops
PCI: 00:1c.4 [8086/1c18] enabled
PCI: 00:1c.5: Disabling device
PCH: Remap PCIe function 6 to 0
PCI: Static device PCI: 00:1c.6 not found, disabling it.
PCI: 00:1c.7: Disabling device
PCH: RPFN 0x76543210 -> 0xf4d3210e
PCH: PCIe map 1c.0 -> 1c.6
PCH: PCIe map 1c.1 -> 1c.0
PCH: PCIe map 1c.2 -> 1c.1
PCH: PCIe map 1c.3 -> 1c.2
PCH: PCIe map 1c.4 -> 1c.3
PCH: PCIe map 1c.6 -> 1c.4
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1c26] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1c4f] enabled
PCI: 00:1f.2 [8086/0000] ops
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
PCI: 00:1f.2 [8086/1c01] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1c22] enabled
PCI: 00:1f.6 [8086/1c24] enabled
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [10de/0dfa] enabled
PCI: 01:00.1 [10de/0bea] enabled
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:01.0 took 657 usecs
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [168c/0030] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpointASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.0 took 346 usecs
PCI: 00:1c.2 scanning...
do_pci_scan_bridge for PCI: 00:1c.2
PCI: pci_scan_bus for bus 03
scan_bus: scanning of bus PCI: 00:1c.2 took 85 usecs
PCI: 00:1c.3 scanning...
do_pci_scan_bridge for PCI: 00:1c.3
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [1180/e823] enabled
PCI: 04:00.1 [1180/e232] enabled
PCI: 04:00.2 [1180/e852] enabled
PCI: 04:00.3 [1180/e832] enabled
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x05 @ 0x50
Capability: type 0x01 @ 0x78
Capability: type 0x10 @ 0x80
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:1c.3 took 1187 usecs
PCI: 00:1f.0 scanning...
scan_lpc_bus for PCI: 00:1f.0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
PNP: 00ff.1 enabled
PNP: 0c31.0 enabled
recv_ec_data: 0x38
recv_ec_data: 0x41
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x38
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
recv_ec_data: 0x00
recv_ec_data: 0x12
EC Firmware ID 8AHT38WW-3.20, Version 0.01C
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x00
recv_ec_data: 0x10
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x20
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x30
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0x00
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0xa7
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
recv_ec_data: 0xc2
recv_ec_data: 0x70
PNP: 00ff.2 enabled
scan_lpc_bus for PCI: 00:1f.0 done
scan_bus: scanning of bus PCI: 00:1f.0 took 6028 usecs
PCI: 00:1f.3 scanning...
scan_smbus for PCI: 00:1f.3
smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
scan_smbus for PCI: 00:1f.3 done
scan_bus: scanning of bus PCI: 00:1f.3 took 204 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 9949 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 10037 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 10975 exit 0
found VGA at PCI: 00:02.0
found VGA at PCI: 01:00.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
More than one caller of pci_ehci_read_resources from PCI: 00:1a.0
PCI: 00:1c.0 read_resources bus 2 link: 0
PCI: 00:1c.0 read_resources bus 2 link: 0 done
PCI: 00:1c.2 read_resources bus 3 link: 0
PCI: 00:1c.2 read_resources bus 3 link: 0 done
PCI: 00:1c.3 read_resources bus 4 link: 0
PCI: 00:1c.3 read_resources bus 4 link: 0 done
PCI: 00:1d.0 EHCI BAR hook registered
PCI: 00:1f.0 read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI: 00:1f.3 read_resources bus 1 link: 0
PCI: 00:1f.3 read_resources bus 1 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: acac
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:01.0 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14
PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c
PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
PCI: 01:00.1
PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
PCI: 00:04.0
PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
PCI: 00:16.0
PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
PCI: 00:1a.0
PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:1c.6
PCI: 00:1c.0 child on link 0 PCI: 02:00.0
PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 02:00.0
PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:1c.3 child on link 0 PCI: 04:00.0
PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 04:00.1
PCI: 04:00.1 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 04:00.2
PCI: 04:00.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 04:00.3
PCI: 04:00.3 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 10
Unknown device path type: 0
Unknown device path type: 0
resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10
Unknown device path type: 0
resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14
Unknown device path type: 0
resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18
PCI: 00:1c.5
PCI: 00:1c.4
PCI: 00:1c.7
PCI: 00:1d.0
PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
PCI: 00:1f.0 child on link 0 PNP: 00ff.1
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
PNP: 00ff.1
PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
PNP: 0c31.0
PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
PNP: 00ff.2
PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
PCI: 00:1f.2
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
PCI: 00:1f.3 child on link 0 I2C: 01:54
PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:5c
I2C: 01:5d
I2C: 01:5e
I2C: 01:5f
PCI: 00:1f.6
PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 24 * [0x0 - 0x7f] io
PCI: 00:01.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
Unknown device path type: 0
18 * [0x0 - 0xfff] io
PCI: 00:1c.3 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:1c.3 1c * [0x1000 - 0x1fff] io
PCI: 00:02.0 20 * [0x2000 - 0x203f] io
PCI: 00:19.0 18 * [0x2040 - 0x205f] io
PCI: 00:1f.2 20 * [0x2060 - 0x207f] io
PCI: 00:1f.2 10 * [0x2080 - 0x2087] io
PCI: 00:1f.2 18 * [0x2088 - 0x208f] io
PCI: 00:1f.2 14 * [0x2090 - 0x2093] io
PCI: 00:1f.2 1c * [0x2094 - 0x2097] io
DOMAIN: 0000 io: base: 2098 size: 2098 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 01:00.0 14 * [0x0 - 0xfffffff] prefmem
PCI: 01:00.0 1c * [0x10000000 - 0x11ffffff] prefmem
PCI: 00:01.0 prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0xffffff] mem
PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem
PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem
PCI: 00:01.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 * [0x0 - 0x1ffff] mem
PCI: 02:00.0 30 * [0x20000 - 0x2ffff] mem
PCI: 00:1c.0 mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
Unknown device path type: 0
14 * [0x0 - 0x7fffff] prefmem
PCI: 00:1c.3 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
Unknown device path type: 0
10 * [0x0 - 0x7fffff] mem
PCI: 04:00.3 10 * [0x800000 - 0x8007ff] mem
PCI: 04:00.0 10 * [0x801000 - 0x8010ff] mem
PCI: 04:00.1 10 * [0x802000 - 0x8020ff] mem
PCI: 04:00.2 10 * [0x803000 - 0x8030ff] mem
PCI: 00:1c.3 mem: base: 803100 size: 900000 align: 22 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 * [0x0 - 0x11ffffff] prefmem
PCI: 00:02.0 18 * [0x20000000 - 0x2fffffff] prefmem
PCI: 00:01.0 20 * [0x30000000 - 0x310fffff] mem
PCI: 00:1c.3 20 * [0x31400000 - 0x31cfffff] mem
PCI: 00:1c.3 24 * [0x32000000 - 0x327fffff] prefmem
PCI: 00:02.0 10 * [0x32800000 - 0x32bfffff] mem
PCI: 00:1c.0 20 * [0x32c00000 - 0x32cfffff] mem
PCI: 00:19.0 10 * [0x32d00000 - 0x32d1ffff] mem
PCI: 00:04.0 10 * [0x32d20000 - 0x32d27fff] mem
PCI: 00:1b.0 10 * [0x32d28000 - 0x32d2bfff] mem
PCI: 00:19.0 14 * [0x32d2c000 - 0x32d2cfff] mem
PCI: 00:1f.6 10 * [0x32d2d000 - 0x32d2dfff] mem
PCI: 00:1f.2 24 * [0x32d2e000 - 0x32d2e7ff] mem
PCI: 00:1a.0 10 * [0x32d2f000 - 0x32d2f3ff] mem
PCI: 00:1d.0 10 * [0x32d30000 - 0x32d303ff] mem
PCI: 00:1f.3 10 * [0x32d31000 - 0x32d310ff] mem
PCI: 00:16.0 10 * [0x32d32000 - 0x32d3200f] mem
DOMAIN: 0000 mem: base: 32d32010 size: 32d32010 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 cf base f8000000 limit fbffffff mem (fixed)
constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
skipping PNP: 00ff.2 at 60 fixed resource, size=0!
skipping PNP: 00ff.2 at 62 fixed resource, size=0!
skipping PNP: 00ff.2 at 64 fixed resource, size=0!
skipping PNP: 00ff.2 at 66 fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit f7ffffff
Setting resources...
DOMAIN: 0000 io: base:167c size:2098 align:12 gran:0 limit:ffff
PCI: 00:01.0 1c * [0x2000 - 0x2fff] io
PCI: 00:1c.3 1c * [0x3000 - 0x3fff] io
PCI: 00:02.0 20 * [0x4000 - 0x403f] io
PCI: 00:19.0 18 * [0x4040 - 0x405f] io
PCI: 00:1f.2 20 * [0x4060 - 0x407f] io
PCI: 00:1f.2 10 * [0x4080 - 0x4087] io
PCI: 00:1f.2 18 * [0x4088 - 0x408f] io
PCI: 00:1f.2 14 * [0x4090 - 0x4093] io
PCI: 00:1f.2 1c * [0x4094 - 0x4097] io
DOMAIN: 0000 io: next_base: 4098 size: 2098 align: 12 gran: 0 done
PCI: 00:01.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 01:00.0 24 * [0x2000 - 0x207f] io
PCI: 00:01.0 io: next_base: 2080 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.2 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.2 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.3 io: base:3000 size:1000 align:12 gran:12 limit:3fff
Unknown device path type: 0
18 * [0x3000 - 0x3fff] io
PCI: 00:1c.3 io: next_base: 4000 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:c0000000 size:32d32010 align:28 gran:0 limit:f7ffffff
PCI: 00:01.0 24 * [0xc0000000 - 0xd1ffffff] prefmem
PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem
PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem
PCI: 00:1c.3 20 * [0xf1400000 - 0xf1cfffff] mem
PCI: 00:1c.3 24 * [0xf2000000 - 0xf27fffff] prefmem
PCI: 00:02.0 10 * [0xf2800000 - 0xf2bfffff] mem
PCI: 00:1c.0 20 * [0xf2c00000 - 0xf2cfffff] mem
PCI: 00:19.0 10 * [0xf2d00000 - 0xf2d1ffff] mem
PCI: 00:04.0 10 * [0xf2d20000 - 0xf2d27fff] mem
PCI: 00:1b.0 10 * [0xf2d28000 - 0xf2d2bfff] mem
PCI: 00:19.0 14 * [0xf2d2c000 - 0xf2d2cfff] mem
PCI: 00:1f.6 10 * [0xf2d2d000 - 0xf2d2dfff] mem
PCI: 00:1f.2 24 * [0xf2d2e000 - 0xf2d2e7ff] mem
PCI: 00:1a.0 10 * [0xf2d2f000 - 0xf2d2f3ff] mem
PCI: 00:1d.0 10 * [0xf2d30000 - 0xf2d303ff] mem
PCI: 00:1f.3 10 * [0xf2d31000 - 0xf2d310ff] mem
PCI: 00:16.0 10 * [0xf2d32000 - 0xf2d3200f] mem
DOMAIN: 0000 mem: next_base: f2d32010 size: 32d32010 align: 28 gran: 0 done
PCI: 00:01.0 prefmem: base:c0000000 size:12000000 align:28 gran:20 limit:d1ffffff
PCI: 01:00.0 14 * [0xc0000000 - 0xcfffffff] prefmem
PCI: 01:00.0 1c * [0xd0000000 - 0xd1ffffff] prefmem
PCI: 00:01.0 prefmem: next_base: d2000000 size: 12000000 align: 28 gran: 20 done
PCI: 00:01.0 mem: base:f0000000 size:1100000 align:24 gran:20 limit:f10fffff
PCI: 01:00.0 10 * [0xf0000000 - 0xf0ffffff] mem
PCI: 01:00.0 30 * [0xf1000000 - 0xf107ffff] mem
PCI: 01:00.1 10 * [0xf1080000 - 0xf1083fff] mem
PCI: 00:01.0 mem: next_base: f1084000 size: 1100000 align: 24 gran: 20 done
PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 mem: base:f2c00000 size:100000 align:20 gran:20 limit:f2cfffff
PCI: 02:00.0 10 * [0xf2c00000 - 0xf2c1ffff] mem
PCI: 02:00.0 30 * [0xf2c20000 - 0xf2c2ffff] mem
PCI: 00:1c.0 mem: next_base: f2c30000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.2 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:1c.2 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 prefmem: base:f2000000 size:800000 align:22 gran:20 limit:f27fffff
Unknown device path type: 0
14 * [0xf2000000 - 0xf27fffff] prefmem
PCI: 00:1c.3 prefmem: next_base: f2800000 size: 800000 align: 22 gran: 20 done
PCI: 00:1c.3 mem: base:f1400000 size:900000 align:22 gran:20 limit:f1cfffff
Unknown device path type: 0
10 * [0xf1400000 - 0xf1bfffff] mem
PCI: 04:00.3 10 * [0xf1c00000 - 0xf1c007ff] mem
PCI: 04:00.0 10 * [0xf1c01000 - 0xf1c010ff] mem
PCI: 04:00.1 10 * [0xf1c02000 - 0xf1c020ff] mem
PCI: 04:00.2 10 * [0xf1c03000 - 0xf1c030ff] mem
PCI: 00:1c.3 mem: next_base: f1c03100 size: 900000 align: 22 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x67ce00000 TOLUD 0x82a00000 TOM 0x600000000
MEBASE 0x5ff800000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0x80000000 size 8M
Available memory below 4GB: 2048M
Available memory above 4GB: 22478M
Adding PCIe config bar base=0xf8000000 size=0x4000000
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:01.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00d1ffffff] size 0x12000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem
PCI: 01:00.0 14 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 01:00.0 1c <- [0x00d0000000 - 0x00d1ffffff] size 0x02000000 gran 0x19 prefmem64
PCI: 01:00.0 24 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io
PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f107ffff] size 0x00080000 gran 0x13 romem
PCI: 01:00.1 10 <- [0x00f1080000 - 0x00f1083fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:02.0 10 <- [0x00f2800000 - 0x00f2bfffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000004000 - 0x000000403f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x00f2d20000 - 0x00f2d27fff] size 0x00008000 gran 0x0f mem64
PCI: 00:16.0 10 <- [0x00f2d32000 - 0x00f2d3200f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00f2d00000 - 0x00f2d1ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00f2d2c000 - 0x00f2d2cfff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000004040 - 0x000000405f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 10 <- [0x00f2d2f000 - 0x00f2d2f3ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00f2d28000 - 0x00f2d2bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00f2c00000 - 0x00f2cfffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:1c.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00f2c00000 - 0x00f2c1ffff] size 0x00020000 gran 0x11 mem64
PCI: 02:00.0 30 <- [0x00f2c20000 - 0x00f2c2ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.0 assign_resources, bus 2 link: 0
PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.2 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:1c.3 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:1c.3 24 <- [0x00f2000000 - 0x00f27fffff] size 0x00800000 gran 0x14 bus 04 prefmem
PCI: 00:1c.3 20 <- [0x00f1400000 - 0x00f1cfffff] size 0x00900000 gran 0x14 bus 04 mem
PCI: 00:1c.3 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00f1c01000 - 0x00f1c010ff] size 0x00000100 gran 0x08 mem
PCI: 04:00.1 10 <- [0x00f1c02000 - 0x00f1c020ff] size 0x00000100 gran 0x08 mem
PCI: 04:00.2 10 <- [0x00f1c03000 - 0x00f1c030ff] size 0x00000100 gran 0x08 mem
PCI: 04:00.3 10 <- [0x00f1c00000 - 0x00f1c007ff] size 0x00000800 gran 0x0b mem
Unknown device path type: 0
missing set_resources
PCI: 00:1c.3 assign_resources, bus 4 link: 0
PCI: 00:1d.0 EHCI Debug Port hook triggered
PCI: 00:1d.0 10 <- [0x00f2d30000 - 0x00f2d303ff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 10 <- [0x00f2d30000 - 0x00f2d303ff] size 0x00000400 gran 0x0a mem
PCI: 00:1d.0 EHCI Debug Port relocated
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000004080 - 0x0000004087] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000004090 - 0x0000004093] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000004088 - 0x000000408f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000004094 - 0x0000004097] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000004060 - 0x000000407f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00f2d2e000 - 0x00f2d2e7ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00f2d31000 - 0x00f2d310ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.3 assign_resources, bus 1 link: 0
PCI: 00:1f.6 10 <- [0x00f2d2d000 - 0x00f2d2dfff] size 0x00001000 gran 0x0c mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: acac
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 167c size 2098 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base c0000000 size 32d32010 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4
DOMAIN: 0000 resource base 100000000 size 57ce00000 align 0 gran 0 limit 0 flags e0004200 index 5
DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
DOMAIN: 0000 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
PCI: 00:01.0 child on link 0 PCI: 01:00.0
PCI: 00:01.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
PCI: 00:01.0 resource base c0000000 size 12000000 align 28 gran 20 limit d1ffffff flags 60081202 index 24
PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit f10fffff flags 60080202 index 20
PCI: 01:00.0
PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit f0ffffff flags 60000200 index 10
PCI: 01:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 14
PCI: 01:00.0 resource base d0000000 size 2000000 align 25 gran 25 limit d1ffffff flags 60001201 index 1c
PCI: 01:00.0 resource base 2000 size 80 align 7 gran 7 limit 207f flags 60000100 index 24
PCI: 01:00.0 resource base f1000000 size 80000 align 19 gran 19 limit f107ffff flags 60002200 index 30
PCI: 01:00.1
PCI: 01:00.1 resource base f1080000 size 4000 align 14 gran 14 limit f1083fff flags 60000200 index 10
PCI: 00:02.0
PCI: 00:02.0 resource base f2800000 size 400000 align 22 gran 22 limit f2bfffff flags 60000201 index 10
PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18
PCI: 00:02.0 resource base 4000 size 40 align 6 gran 6 limit 403f flags 60000100 index 20
PCI: 00:04.0
PCI: 00:04.0 resource base f2d20000 size 8000 align 15 gran 15 limit f2d27fff flags 60000201 index 10
PCI: 00:16.0
PCI: 00:16.0 resource base f2d32000 size 10 align 12 gran 4 limit f2d3200f flags 60000201 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:19.0
PCI: 00:19.0 resource base f2d00000 size 20000 align 17 gran 17 limit f2d1ffff flags 60000200 index 10
PCI: 00:19.0 resource base f2d2c000 size 1000 align 12 gran 12 limit f2d2cfff flags 60000200 index 14
PCI: 00:19.0 resource base 4040 size 20 align 5 gran 5 limit 405f flags 60000100 index 18
PCI: 00:1a.0
PCI: 00:1a.0 resource base f2d2f000 size 400 align 12 gran 10 limit f2d2f3ff flags 60000200 index 10
PCI: 00:1b.0
PCI: 00:1b.0 resource base f2d28000 size 4000 align 14 gran 14 limit f2d2bfff flags 60000201 index 10
PCI: 00:1c.6
PCI: 00:1c.0 child on link 0 PCI: 02:00.0
PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:1c.0 resource base f2c00000 size 100000 align 20 gran 20 limit f2cfffff flags 60080202 index 20
PCI: 02:00.0
PCI: 02:00.0 resource base f2c00000 size 20000 align 17 gran 17 limit f2c1ffff flags 60000201 index 10
PCI: 02:00.0 resource base f2c20000 size 10000 align 16 gran 16 limit f2c2ffff flags 60002200 index 30
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 00:1c.3 child on link 0 PCI: 04:00.0
PCI: 00:1c.3 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
PCI: 00:1c.3 resource base f2000000 size 800000 align 22 gran 20 limit f27fffff flags 60081202 index 24
PCI: 00:1c.3 resource base f1400000 size 900000 align 22 gran 20 limit f1cfffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base f1c01000 size 100 align 12 gran 8 limit f1c010ff flags 60000200 index 10
PCI: 04:00.1
PCI: 04:00.1 resource base f1c02000 size 100 align 12 gran 8 limit f1c020ff flags 60000200 index 10
PCI: 04:00.2
PCI: 04:00.2 resource base f1c03000 size 100 align 12 gran 8 limit f1c030ff flags 60000200 index 10
PCI: 04:00.3
PCI: 04:00.3 resource base f1c00000 size 800 align 12 gran 11 limit f1c007ff flags 60000200 index 10
Unknown device path type: 0
Unknown device path type: 0
resource base f1400000 size 800000 align 22 gran 22 limit f1bfffff flags 40000200 index 10
Unknown device path type: 0
resource base f2000000 size 800000 align 22 gran 22 limit f27fffff flags 40001200 index 14
Unknown device path type: 0
resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 40000100 index 18
PCI: 00:1c.5
PCI: 00:1c.4
PCI: 00:1c.7
PCI: 00:1d.0
PCI: 00:1d.0 resource base f2d30000 size 400 align 12 gran 10 limit f2d303ff flags 60000200 index 10
PCI: 00:1f.0 child on link 0 PNP: 00ff.1
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
PNP: 00ff.1
PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
PNP: 0c31.0
PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
PNP: 00ff.2
PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
PCI: 00:1f.2
PCI: 00:1f.2 resource base 4080 size 8 align 3 gran 3 limit 4087 flags 60000100 index 10
PCI: 00:1f.2 resource base 4090 size 4 align 2 gran 2 limit 4093 flags 60000100 index 14
PCI: 00:1f.2 resource base 4088 size 8 align 3 gran 3 limit 408f flags 60000100 index 18
PCI: 00:1f.2 resource base 4094 size 4 align 2 gran 2 limit 4097 flags 60000100 index 1c
PCI: 00:1f.2 resource base 4060 size 20 align 5 gran 5 limit 407f flags 60000100 index 20
PCI: 00:1f.2 resource base f2d2e000 size 800 align 12 gran 11 limit f2d2e7ff flags 60000200 index 24
PCI: 00:1f.3 child on link 0 I2C: 01:54
PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
PCI: 00:1f.3 resource base f2d31000 size 100 align 12 gran 8 limit f2d310ff flags 60000201 index 10
I2C: 01:54
I2C: 01:55
I2C: 01:56
I2C: 01:57
I2C: 01:5c
I2C: 01:5d
I2C: 01:5e
I2C: 01:5f
PCI: 00:1f.6
PCI: 00:1f.6 resource base f2d2d000 size 1000 align 12 gran 12 limit f2d2dfff flags 60000201 index 10
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 15973 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 07
PCI: 00:02.0 subsystem <- 0000/0000
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 cmd <- 02
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 0000/0000
PCI: 00:19.0 cmd <- 103
PCI: 00:1a.0 subsystem <- 0000/0000
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 0000/0000
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 0000/0000
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.2 bridge ctrl <- 0003
PCI: 00:1c.2 subsystem <- 0000/0000
PCI: 00:1c.2 cmd <- 100
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 subsystem <- 0000/0000
PCI: 00:1c.3 cmd <- 107
PCI: 00:1d.0 subsystem <- 0000/0000
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 0000/0000
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 0000/0000
PCI: 00:1f.3 cmd <- 103
PCI: 00:1f.6 cmd <- 02
PCI: 01:00.0 cmd <- 03
PCI: 01:00.1 cmd <- 02
PCI: 02:00.0 cmd <- 02
PCI: 04:00.0 cmd <- 06
PCI: 04:00.1 cmd <- 06
PCI: 04:00.2 cmd <- 06
PCI: 04:00.3 cmd <- 02
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 651 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 10 usecs
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
Setting up SMI for CPU
Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x00038000
Adjusting 00038002: 0x00000024 -> 0x00038024
Adjusting 0003801d: 0x0000003c -> 0x0003803c
Adjusting 00038026: 0x00000024 -> 0x00038024
Adjusting 00038054: 0x000000d8 -> 0x000380d8
Adjusting 00038066: 0x00000160 -> 0x00038160
Adjusting 0003806d: 0x000000c0 -> 0x000380c0
Adjusting 00038075: 0x000000c4 -> 0x000380c4
Adjusting 0003807e: 0x000000d0 -> 0x000380d0
Adjusting 00038085: 0x000000cc -> 0x000380cc
Adjusting 0003808b: 0x000000c8 -> 0x000380c8
SMM Module: stub loaded at 00038000. Will call 00115f26(00135900)
Installing SMM handler to 0x80000000
Loading module at 80010000 with entry 8001056d. filesize: 0x18d8 memsize: 0x58f8
Processing 75 relocs. Offset value of 0x80010000
Adjusting 80010036: 0x000017dc -> 0x800117dc
Adjusting 80010055: 0x000017dc -> 0x800117dc
Adjusting 80010108: 0x000017dc -> 0x800117dc
Adjusting 80010198: 0x00001736 -> 0x80011736
Adjusting 800104bc: 0x000018d8 -> 0x800118d8
Adjusting 800104d6: 0x000018e0 -> 0x800118e0
Adjusting 800104ed: 0x000018e0 -> 0x800118e0
Adjusting 8001053a: 0x000018d0 -> 0x800118d0
Adjusting 80010550: 0x00001820 -> 0x80011820
Adjusting 80010576: 0x000018d8 -> 0x800118d8
Adjusting 80010584: 0x000018d8 -> 0x800118d8
Adjusting 80010591: 0x000018c0 -> 0x800118c0
Adjusting 8001059c: 0x000018c0 -> 0x800118c0
Adjusting 800105b0: 0x000018c4 -> 0x800118c4
Adjusting 800105b6: 0x000018dc -> 0x800118dc
Adjusting 800105be: 0x000018c4 -> 0x800118c4
Adjusting 800105db: 0x000018dc -> 0x800118dc
Adjusting 800105e4: 0x000018c0 -> 0x800118c0
Adjusting 80010700: 0x0000173f -> 0x8001173f
Adjusting 8001080e: 0x000018cc -> 0x800118cc
Adjusting 80010837: 0x000018cc -> 0x800118cc
Adjusting 80010854: 0x000018cc -> 0x800118cc
Adjusting 8001087d: 0x000018c8 -> 0x800118c8
Adjusting 8001089a: 0x000018cc -> 0x800118cc
Adjusting 800108c0: 0x000018c8 -> 0x800118c8
Adjusting 80010978: 0x000018cc -> 0x800118cc
Adjusting 8001097d: 0x000018c8 -> 0x800118c8
Adjusting 8001098c: 0x000017c8 -> 0x800117c8
Adjusting 80010ca3: 0x000018e4 -> 0x800118e4
Adjusting 80010cd2: 0x000018e8 -> 0x800118e8
Adjusting 80010ce5: 0x000018e4 -> 0x800118e4
Adjusting 80010d08: 0x000018e8 -> 0x800118e8
Adjusting 80010dcb: 0x000018e4 -> 0x800118e4
Adjusting 80011006: 0x000018e8 -> 0x800118e8
Adjusting 800111f5: 0x000018e8 -> 0x800118e8
Adjusting 800112d7: 0x000018d0 -> 0x800118d0
Adjusting 800112e7: 0x000018d0 -> 0x800118d0
Adjusting 800112fc: 0x000018d0 -> 0x800118d0
Adjusting 8001131d: 0x000018d0 -> 0x800118d0
Adjusting 8001134c: 0x000018d0 -> 0x800118d0
Adjusting 8001136b: 0x000018d0 -> 0x800118d0
Adjusting 8001137e: 0x000018f4 -> 0x800118f4
Adjusting 800113c2: 0x000018ec -> 0x800118ec
Adjusting 800113df: 0x000018ec -> 0x800118ec
Adjusting 800113fd: 0x000018f4 -> 0x800118f4
Adjusting 80011403: 0x000018f0 -> 0x800118f0
Adjusting 80011410: 0x000018d0 -> 0x800118d0
Adjusting 80011436: 0x000018d0 -> 0x800118d0
Adjusting 8001148b: 0x000018f0 -> 0x800118f0
Adjusting 800114e2: 0x000017ab -> 0x800117ab
Adjusting 800114fd: 0x000018d0 -> 0x800118d0
Adjusting 8001151e: 0x00001800 -> 0x80011800
Adjusting 80011523: 0x000018f0 -> 0x800118f0
Adjusting 800115e6: 0x000018d0 -> 0x800118d0
Adjusting 80011614: 0x000018d0 -> 0x800118d0
Adjusting 8001165d: 0x000018d0 -> 0x800118d0
Adjusting 800116fb: 0x000018f0 -> 0x800118f0
Adjusting 8001170f: 0x000018d0 -> 0x800118d0
Adjusting 800117c0: 0x00001720 -> 0x80011720
Adjusting 800117c8: 0x00000021 -> 0x80010021
Adjusting 800117cc: 0x00001720 -> 0x80011720
Adjusting 800117d4: 0x00000092 -> 0x80010092
Adjusting 800117e0: 0x000017ec -> 0x800117ec
Adjusting 800117ec: 0x000002d2 -> 0x800102d2
Adjusting 800117f0: 0x000002de -> 0x800102de
Adjusting 800117f4: 0x000002e1 -> 0x800102e1
Adjusting 80011830: 0x000014cc -> 0x800114cc
Adjusting 80011834: 0x0000132d -> 0x8001132d
Adjusting 80011840: 0x0000140d -> 0x8001140d
Adjusting 80011844: 0x000012d4 -> 0x800112d4
Adjusting 80011848: 0x000012f5 -> 0x800112f5
Adjusting 8001184c: 0x000012f0 -> 0x800112f0
Adjusting 80011854: 0x00001433 -> 0x80011433
Adjusting 80011858: 0x000012e4 -> 0x800112e4
Adjusting 80011874: 0x00001476 -> 0x80011476
Loading module at 80008000 with entry 80008000. filesize: 0x160 memsize: 0x160
Processing 10 relocs. Offset value of 0x80008000
Adjusting 80008002: 0x00000024 -> 0x80008024
Adjusting 8000801d: 0x0000003c -> 0x8000803c
Adjusting 80008026: 0x00000024 -> 0x80008024
Adjusting 80008054: 0x000000d8 -> 0x800080d8
Adjusting 80008066: 0x00000160 -> 0x80008160
Adjusting 8000806d: 0x000000c0 -> 0x800080c0
Adjusting 80008075: 0x000000c4 -> 0x800080c4
Adjusting 8000807e: 0x000000d0 -> 0x800080d0
Adjusting 80008085: 0x000000cc -> 0x800080cc
Adjusting 8000808b: 0x000000c8 -> 0x800080c8
SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 80007800 rel16 0x07fd
SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd
SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd
SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd
SMM Module: placing jmp sequence at 80006800 rel16 0x17fd
SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd
SMM Module: stub loaded at 80008000. Will call 8001056d(00000000)
Initializing southbridge SMI... ... pmbase = 0x0500
SMI_STS: MCSMI PM1
PM1_STS: WAK PWRBTN TMROF
GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI5 GPI4 GPI3 GPI1 GPI0
TCO_STS: INTRD_DET
... raise SMI#
In relocation handler: cpu 0
New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Relocation complete.
Locking SMM.
Initializing CPU #0
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000c0000000 size 0x40000000 type 0
0x00000000c0000000 - 0x00000000d2000000 size 0x12000000 type 1
0x00000000d2000000 - 0x00000000e0000000 size 0x0e000000 type 0
0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1
0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0
0x0000000100000000 - 0x000000067ce00000 size 0x57ce00000 type 6
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR addr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc1 set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd2-0xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTRR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type @ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 8/11.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 1
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ffe000000 type 1
MTRR: 3 base 0x00000000d2000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d4000000 mask 0x0000000ffc000000 type 0
MTRR: 5 base 0x00000000d8000000 mask 0x0000000ff8000000 type 0
MTRR: 6 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1
MTRR: 7 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x00 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
Turbo is available but hidden
Turbo has been enabled
CPU: 0 has 4 cores, 2 threads per core
CPU: 0 has core 1
CPU1: stack_base 0012f000, stack_end 0012fff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
In relocation handler: cpu 1
New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: 0 has core 2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x01 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #1 initialized
CPU2: stack_base 0012e000, stack_end 0012eff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
In relocation handler: cpu 2
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 2.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 3
Initializing CPU #2
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x02 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #2 initialized
CPU3: stack_base 0012d000, stack_end 0012dff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
In relocation handler: cpu 3
New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 4
Initializing CPU #3
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x03 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #3 initialized
CPU4: stack_base 0012c000, stack_end 0012cff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 4.
After apic_write.
In relocation handler: cpu 4
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 4.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 5
Initializing CPU #4
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x04 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #4 initialized
CPU5: stack_base 0012b000, stack_end 0012bff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 5.
After apic_write.
In relocation handler: cpu 5
New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 5.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 6
Initializing CPU #5
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x05 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #5 initialized
CPU6: stack_base 0012a000, stack_end 0012aff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 6.
After apic_write.
In relocation handler: cpu 6
Startup point 1.
Waiting for send to finish...
+New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00
Sending STARTUP #2 to 6.
After apic_write.
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 7
Initializing CPU #6
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x0
microcode: updated to revision 0x1b date=2014-05-29
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x06 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #6 initialized
CPU7: stack_base 00129000, stack_end 00129ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 7.
After apic_write.
In relocation handler: cpu 7
New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00
Writing SMRR. base = 0x80000006, mask=0xff800800
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 7.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU #0 initialized
Waiting for 1 CPUS to stop
Initializing CPU #7
CPU: vendor Intel device 306a9
CPU: family 06, model 3a, stepping 09
Enabling cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 80 size 5800
microcode: sig=0x306a9 pf=0x10 revision=0x1b
CPU: Intel(R) Core(TM) i7-3940XM CPU @ 3.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local APIC... apic_id: 0x07 done.
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 3000
CPU #7 initialized
All AP CPUs stopped (660 loops)
CPU0: stack: 00130000 - 00131000, lowest used address 00130aa0, stack used: 1376 bytes
CPU1: stack: 0012f000 - 00130000, lowest used address 0012fc64, stack used: 924 bytes
CPU2: stack: 0012e000 - 0012f000, lowest used address 0012ec64, stack used: 924 bytes
CPU3: stack: 0012d000 - 0012e000, lowest used address 0012dc64, stack used: 924 bytes
CPU4: stack: 0012c000 - 0012d000, lowest used address 0012cc64, stack used: 924 bytes
CPU5: stack: 0012b000 - 0012c000, lowest used address 0012bc64, stack used: 924 bytes
CPU6: stack: 0012a000 - 0012b000, lowest used address 0012ac64, stack used: 924 bytes
CPU7: stack: 00129000 - 0012a000, lowest used address 00129c64, stack used: 924 bytes
CPU_CLUSTER: 0 init finished in 188947 usecs
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling PEG60.
Set BIOS_RESET_CPL
CPU TDP: 55 Watts
PCI: 00:00.0 init finished in 1016 usecs
PCI: 00:02.0 init ...
GT Power Management Init
IVB GT2 35W Power Meter Weights
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 147 usecs
PCI: 00:04.0 init ...
PCI: 00:04.0 init finished in 0 usecs
PCI: 00:16.0 init ...
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : YES
ME: Manufacturing Mode : YES
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : Host Communication
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : Host communication established
ME: BIOS path: Normal
ME: Extend SHA-256: 8e5a7f7302a670b1c63946e89940074b55750c18ff28106b53bc7440f89457e3
ME: Firmware Version 7.1.1214.80 (code) 7.1.1214.80 (recovery)
ME Capability: Full Network manageability : disabled
ME Capability: Regular Network manageability : disabled
ME Capability: Manageability : disabled
ME Capability: Small business technology : disabled
ME Capability: Level III manageability : enabled
ME Capability: IntelR Anti-Theft (AT) : enabled
ME Capability: IntelR Capability Licensing Service (CLS) : enabled
ME Capability: IntelR Power Sharing Technology (MPC) : enabled
ME Capability: ICC Over Clocking : enabled
ME Capability: Protected Audio Video Path (PAVP) : enabled
ME Capability: IPV6 : disabled
ME Capability: KVM Remote Control (KVM) : disabled
ME Capability: Outbreak Containment Heuristic (OCH) : disabled
ME Capability: Virtual LAN (VLAN) : enabled
ME Capability: TLS : disabled
ME Capability: Wireless LAN (WLAN) : disabled
PCI: 00:16.0 init finished in 6212 usecs
PCI: 00:19.0 init ...
PCI: 00:19.0 init finished in 0 usecs
PCI: 00:1a.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 13 usecs
PCI: 00:1b.0 init ...
Azalia: base = f2d28000
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862805
Azalia: No verb!
Azalia: Initializing codec #0
Azalia: codec viddid: 14f1506e
Azalia: verb_size: 52
Azalia: verb loaded.
PCI: 00:1b.0 init finished in 4308 usecs
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 8 usecs
PCI: 00:1c.2 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.2 init finished in 8 usecs
PCI: 00:1c.3 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.3 init finished in 10 usecs
PCI: 00:1d.0 init ...
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 13 usecs
PCI: 00:1f.0 init ...
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
reg 0x0000: 0x02000000
reg 0x0001: 0x00170020
reg 0x0002: 0x00170020
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
Set power off after power failure.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
NMI sources enabled.
CougarPoint PM init
rtc_failed = 0x0
RTC Init
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
pch_spi_init
PCI: 00:1f.0 init finished in 757 usecs
PCI: 00:1f.2 init ...
SATA: Initializing...
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
SATA: Controller in AHCI mode.
ABAR: f2d2e000
PCI: 00:1f.2 init finished in 283 usecs
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 7 usecs
PCI: 00:1f.6 init ...
PCI: 00:1f.6 init finished in 0 usecs
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 0 usecs
PCI: 01:00.1 init ...
PCI: 01:00.1 init finished in 0 usecs
PCI: 02:00.0 init ...
PCI: 02:00.0 init finished in 0 usecs
PCI: 04:00.0 init ...
PCI: 04:00.0 init finished in 0 usecs
PCI: 04:00.1 init ...
PCI: 04:00.1 init finished in 0 usecs
PCI: 04:00.2 init ...
PCI: 04:00.2 init finished in 0 usecs
PCI: 04:00.3 init ...
PCI: 04:00.3 init finished in 0 usecs
PNP: 00ff.2 init ...
PNP: 00ff.2 init finished in 0 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
I2C: 01:54 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
I2C: 01:55 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
I2C: 01:56 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
I2C: 01:57 init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
Locking EEPROM RFID
init EEPROM done
I2C: 01:5c init finished in 26691 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
I2C: 01:5d init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
I2C: 01:5e init finished in 1 usecs
smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
I2C: 01:5f init finished in 1 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.6: enabled 0
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1c.4: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PNP: 00ff.1: enabled 1
PNP: 0c31.0: enabled 1
PNP: 00ff.2: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
I2C: 01:54: enabled 1
I2C: 01:55: enabled 1
I2C: 01:56: enabled 1
I2C: 01:57: enabled 1
I2C: 01:5c: enabled 1
I2C: 01:5d: enabled 1
I2C: 01:5e: enabled 1
I2C: 01:5f: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:1f.6: enabled 1
PCI: 01:00.0: enabled 1
PCI: 01:00.1: enabled 1
PCI: 02:00.0: enabled 1
PCI: 04:00.0: enabled 1
PCI: 04:00.1: enabled 1
PCI: 04:00.2: enabled 1
PCI: 04:00.3: enabled 1
Unknown device path type: 0
: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
APIC: 06: enabled 1
APIC: 07: enabled 1
BS: BS_DEV_INIT times (us): entry 6 run 228656 exit 0
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 5 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
Updating MRC cache data.
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset 2fec0 size 10000
find_current_mrc_cache_local: No valid MRC cache found.
SF: Detected W25Q64 with sector size 0x1000, total 0x800000
Need to erase the MRC cache region of 65536 bytes at ff9b0000
SF: Successfully erased 65536 bytes @ 0x1b0000
Finally: write MRC cache update to flash at ff9b0000
Successfully wrote MRC cache
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 6a40 size 3617
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7feb0000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * IGD OpRegion
GET_VBIOS: 43a8 4e86 5b c1 6b
VBIOS not found.
ACPI: * FADT
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Found 1 CPU(s) with 8 core(s) each.
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
PSS: 3001MHz power 55000 control 0x2700 status 0x2700
PSS: 3000MHz power 55000 control 0x1e00 status 0x1e00
PSS: 2400MHz power 41008 control 0x1800 status 0x1800
PSS: 2000MHz power 32564 control 0x1400 status 0x1400
PSS: 1600MHz power 24829 control 0x1000 status 0x1000
PSS: 1200MHz power 17710 control 0xc00 status 0xc00
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TCPA
TCPA log created at 7fe9d000
ACPI: added table 4/32, length now 52
ACPI: * MADT
ACPI: added table 5/32, length now 56
current = 7feb6320
ACPI: * DMAR
ACPI: added table 6/32, length now 60
current = 7feb63d0
ACPI: * HPET
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 25616 bytes.
smbios_write_tables: 7fe9c000
recv_ec_data: 0x38
recv_ec_data: 0x41
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x38
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
Create SMBIOS type 17
Root Device (LENOVO ThinkPad W520)
CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
APIC: 00 (unknown)
APIC: acac (Intel SandyBridge/IvyBridge CPU)
DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
PNP: 0c31.0 (LPC TPM)
PNP: 00ff.2 (Lenovo H8 EC)
PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
I2C: 01:54 (AT24RF08C)
I2C: 01:55 (AT24RF08C)
I2C: 01:56 (AT24RF08C)
I2C: 01:57 (AT24RF08C)
I2C: 01:5c (AT24RF08C)
I2C: 01:5d (AT24RF08C)
I2C: 01:5e (AT24RF08C)
I2C: 01:5f (AT24RF08C)
PCI: 00:04.0 (unknown)
PCI: 00:1f.6 (unknown)
PCI: 01:00.0 (unknown)
PCI: 01:00.1 (unknown)
PCI: 02:00.0 (unknown)
PCI: 04:00.0 (unknown)
PCI: 04:00.1 (unknown)
PCI: 04:00.2 (unknown)
PCI: 04:00.3 (unknown)
Unknown device path type: 0
(unknown)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
APIC: 06 (unknown)
APIC: 07 (unknown)
SMBIOS tables: 706 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3ff1
Writing coreboot table at 0x7fed4000
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 61c0 size 810
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fe9bfff: RAM
4. 000000007fe9c000-000000007fffffff: CONFIGURATION TABLES
5. 0000000080000000-00000000829fffff: RESERVED
6. 00000000f8000000-00000000fbffffff: RESERVED
7. 00000000fed40000-00000000fed44fff: RESERVED
8. 00000000fed90000-00000000fed91fff: RESERVED
9. 0000000100000000-000000067cdfffff: RAM
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
FMAP: Found "FLASH" version 1.1 at 180000.
FMAP: base = ff800000 size = 800000 #areas = 3
Wrote coreboot table at: 7fed4000, 0xb74 bytes, checksum c96d
coreboot table: 2956 bytes.
IMD ROOT 0. 7ffff000 00001000
IMD SMALL 1. 7fffe000 00001000
CONSOLE 2. 7ffde000 00020000
TIME STAMP 3. 7ffdd000 00000400
MRC DATA 4. 7ffdc000 000005b0
ACPI RESUME 5. 7fedc000 00100000
COREBOOT 6. 7fed4000 00008000
ACPI 7. 7feb0000 00024000
ACPI GNVS 8. 7feaf000 00001000
4f444749 9. 7fead000 00002000
TCPA LOG 10. 7fe9d000 00010000
SMBIOS 11. 7fe9c000 00000800
IMD small region:
IMD ROOT 0. 7fffec00 00000400
CAR GLOBALS 1. 7fffea40 000001c0
USBDEBUG 2. 7fffe9e0 00000058
MEM INFO 3. 7fffe880 00000141
ROMSTAGE 4. 7fffe860 00000004
GDT 5. 7fffe660 00000200
BS: BS_WRITE_TABLES times (us): entry 425988 run 25985 exit 0
CBFS: 'Master Header Locator' located CBFS at [180100:7fffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 62940 size f65f
Loading segment from ROM address 0xff9e2a78
code (compression=1)
New segment dstaddr 0xe31e0 memsize 0x1ce20 srcaddr 0xff9e2ab0 filesize 0xf627
Loading segment from ROM address 0xff9e2a94
Entry Point 0x000ff06e
Payload being loaded at below 1MiB without region being marked as RAM usable.
Bounce Buffer at 7fe28000, 471776 bytes
Loading Segment: addr: 0x00000000000e31e0 memsz: 0x000000000001ce20 filesz: 0x000000000000f627
lb: [0x0000000000100000, 0x0000000000139970)
Post relocation: addr: 0x00000000000e31e0 memsz: 0x000000000001ce20 filesz: 0x000000000000f627
using LZMA
[ 0x000e31e0, 00100000, 0x00100000) <- ff9e2ab0
dest 000e31e0, end 00100000, bouncebuffer 7fe28000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 18111 exit 0
PCH watchdog disabled
Jumping to boot code at 000ff06e(7fed4000)
CPU0: stack: 00130000 - 00131000, lowest used address 00130aa0, stack used: 1376 bytes
entry = 0x000ff06e
lb_start = 0x00100000
lb_size = 0x00039970
buffer = 0x7fe28000
SeaBIOS (version rel-1.10.0-0-gd7adf60)
BUILD: gcc: (coreboot toolchain v1.43 August 31st, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
Found coreboot cbmem console @ 7ffde000
Found mainboard LENOVO ThinkPad W520
Relocating init from 0x000e4740 to 0x7fe4fe20 (size 49472)
Found CBFS header at 0xff980138
multiboot: eax=0, ebx=0
Found 23 PCI devices (max PCI bus is 04)
Copying SMBIOS entry point from 0x7fe9c000 to 0x000f0860
Copying ACPI RSDP from 0x7feb0000 to 0x000f0830
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.10.0-0-gd7adf60)
Machine UUID 56196001-5261-11cb-9404-b9288c86426a
EHCI init on dev 00:1a.0 (regs=0xf2d2f020)
EHCI init on dev 00:1d.0 (regs=0xf2d30020)
AHCI controller at 00:1f.2, iobase 0xf2d2e000, irq 10
Searching bootorder for: /pci at i0cf8/pci-bridge at 1c,3/*@0
Found 0 lpt ports
Found 0 serial ports
Searching bootorder for: /rom at img/memtest
Searching bootorder for: /rom at img/coreinfo
Searching bootorder for: /rom at img/smcoreinfo
Discarding ps2 data aa (status=11)
Searching bootorder for: /pci at i0cf8/*@1f,2/drive at 1/disk at 0
AHCI/1: Set transfer mode to UDMA-6
AHCI/1: registering: "AHCI/1: Samsung SSD 850 EVO 500GB ATA-9 Hard-Disk (440 GiBytes)"
Initialized USB HUB (0 ports used)
Initialized USB HUB (0 ports used)
PS2 keyboard initialized
All threads complete.
Scan for option roms
Press ESC for boot menu.
Searching bootorder for: HALT
drive 0x000f07c0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=922748928
Space available for UMB: cf800-ee800, f0000-f07c0
Returned 253952 bytes of ZoneHigh
e820 map has 9 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007fe9a000 = 1 RAM
4: 000000007fe9a000 - 0000000082a00000 = 2 RESERVED
5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
8: 0000000100000000 - 000000067ce00000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
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