[coreboot] ThinkPad x220 - Status
naomoreira at gmail.com
Wed May 25 16:26:32 CEST 2016
I would like to update you with my current x220 status:
1) *DDR3 Speed:*
- My goal was to get 1866Mhz DDR3 speed (tCK = 933Mhz);
- I'm using 2 of these modules: CRUCIAL_CT8G3S186DM.M16F
- With default coreboot-4.4 I was getting just 1333MHz (tCK = 666MHz):
- After editing coreboot source (check below), I'm getting 1600Mhz (tCK
= 800MHz): dmidecode <http://pastebin.com/KR0RVZ0z>*;*
- The patch is very simple (Thanks a lot for your help Iru):
- Edit src/northbridge/intel/sandybridge/raminit.c;
- Add: 'return TCK_933MHZ;' to the very beginning of
- This avoid automatic detection of the capabilities and makes
coreboot(?) think that the min_freq is 1866MHz;
- As I said, doing this gave me just 1600MHz so, as a paranoid
check, I decided to use 'return TCK_1066MHZ;'
- Using tCK = 1066MHz also gave me just 1600MHz (my current
firmware build is using tCK = 1066MHz);
- Apparently, the patch works and that makes me happy :) So the
question is: Why 1866MHz is not being applied?:
- I found a better tool to get DIMM info: command is decode-dimms,
from i2c-tools package (don't forget to load eeprom module);
- With decode-dimms I get much more info than with dmidecode. Current
output of my x220 is here <http://pastebin.com/fMDW9XFw>;
- In this output we can see: Maximum module speed: 1777 MHz
- This makes think these Crucial modules cannot reach 1866MHz and
that's why I'm getting only 1600MHz. Unfortunately I don't
have any other
1866MHz modules to test;
- In resume, I think there's nothing more we can do here. Good
progress anyway. Thanks everyone.
2) *Battery Charging Thresholds:*
- tp_smapi is not supported;
- tpacpi-bat doesn't work either:
- [~]$ tpacpi-bat -v -g ST 1
Error: AE_NOT_FOUND for ASL base: \_SB.PCI0.LPCB.EC.HKEY
Error: AE_NOT_FOUND at /usr/bin/tpacpi-bat line 409.
- I think '\_SB.PCI0.LPCB.EC.HKEY' is not found...
- acpidump is here <http://pastebin.com/G3UZQNbX>;
- In TLP I get: tpacpi-bat = inactive (unsupported hardware);
- Any ideas here?
3) *Internal MIC device:*
- I cannot mute internal MIC (it was possible with official firmware);
- Even if I try to mute it using pavucontrol, the MIC mute led never
- Any ideas here?
I still have some tests and validations ongoing, but the issues present are
the only open topics at the moment.
Hope it helps and I'm looking forward for your feedback.
Thanks in advance.
On Wed, May 25, 2016 at 12:06 PM, Nuno Moreira <naomoreira at gmail.com> wrote:
> Hello Zoran, Hello everybody,
> Thanks for your reply Zoran.
> I'll try to give all the details about it. Maybe you are missing some
> important detail.
> 1 - Laptop was with official BIOS_1.29 / EC_1.20;
> 2 - From windows, updated to official BIOS_1.40 / EC_1.24;
> 3 - From windows, installed custom 8duj26us_NWL_ADV_AES_PM_Speedo;
> 4 - Custom BIOS unlocked Advanced Menu (with tons of chipset related
> 5 - 2x8GB DDR3-1866Mhz modules installed. Changed RAM speed to 1866Mhz in
> 6 - Booted to Archlinux and dmidecode reported 1333Mhz as RAM speed;
> 7 - I went back to BIOS and changed RAM speed to Auto and noticed that
> SR-IOV was not activated for PCI, so I decided to activate it since I plan
> to play a little with kvm and stuff (If I recall correctly, these were the
> only 2 changes that bricked the system).
> 8 - Save and exit: BIOS bricked. Infinite boot/restart loop until I remove
> 9 - Tried to remove all the hardware and clear CMOS. Nothing worked.
> Always in boot loop.
> I still have the flashrom read dump of this bricked unofficial BIOS.
> Let me know i you want the dump. Maybe you can get some info from it.
> *Possible stupid question:* I tried to find a solution to recover this
> bricked BIOS and flash it back but I don't have the know how to do it. Do
> you think it is possible to unbrick the BIOS from the dump and flash it
> *PS:* I've made some progress with coreboot in the meantime (good and bad
> news). Will reply to the mailing-list after complete other tests.
> Thanks in advance.
> On Tue, May 24, 2016 at 8:27 PM, Zoran Stojsavljevic <
> zoran.stojsavljevic at gmail.com> wrote:
>> Hello Nuno,
>> Very interesting use case, I should say.
>> *> 1) Init:*
>> > --------
>> > Recently I bought a refurbished x220 and flashed it with a custom BIOS
>> (Lenovo ThinkPad
>> > x220_1.40-(8DET70WW)-8duj26us_NWL_ADV_AES_PM_Speedo) because I wanted
>> to unlock the RAM speed
>> > to be 1866MHz (max RAM speed is locked to 1333Mhz in official BIOS),
>> white-list some Wi-Fi
>> > cards, Advanced Chipset Config menu, etc.
>> > This custom BIOS worked perfectly until I changed some settings related
>> with Intel VT-x. If
>> > I recall correctly, I activated SR-IOV for PCI-E, saved and exited and
>> after that x220 =
>> > BRICKED.
>> > I tried every typical troubleshooting/workaround (Removing as much HW
>> as possible, unplug
>> > BIOS battery for hours, etc), nothing worked.
>> This is peculiar... How SR-IOV feature can break the BIOS??? Never saw
>> such or similar brick.
>> Taking to account that introduced custom BIOS (Lenovo ThinkPad
>> x220_1.40-(8DET70WW)-8duj26us_NWL_ADV_AES_PM_Speedo) added (probably)
>> additional few Memory Reference Code algorithms to make DDR3 work @
>> 1866MHz, I have no clue how these two parameters are connected/in
>> But I'll try to investigate this use case. Not (at all) in connection
>> with Coreboot, rather I would like to understand why SNB BIOS behaves like
>> this? Maybe I can learn much more out of this?!
>> I'll move this to other (BIOS based) forum, and try to see if there are
>> more experienced BIOS people to put some light on/demystify this problem?
>> It is, after all, Sandy Bridge CORe:
>> Let me see what I can dig out of this? ;-)
>> Best Regards,
>> On Mon, May 23, 2016 at 3:00 PM, Nuno Moreira <naomoreira at gmail.com>
>>> Hello, everyone.
>>> First of all, I would like to thanks and to congratulate all the
>>> community who helps to develop and to optimize this great project. Keep it
>>> up :)
>>> I would appreciate if you can give me some opinions or point me to
>>> someone who will, regarding the Open Issues I present below (3.1 and 3.2).
>>> Trying to give you a brief contextualization of my status before and
>>> after Coreboot.
>>> *1) Init:*
>>> Recently I bought a refurbished x220 and flashed it with a custom BIOS
>>> (Lenovo ThinkPad x220_1.40-(8DET70WW)-8duj26us_NWL_ADV_AES_PM_Speedo)
>>> because I wanted to unlock the RAM speed to be 1866MHz (max RAM speed is
>>> locked to 1333Mhz in official BIOS), white-list some Wi-Fi cards, Advanced
>>> Chipset Config menu, etc.
>>> This custom BIOS worked perfectly until I changed some settings related
>>> with Intel VT-x. If I recall correctly, I activated SR-IOV for PCI-E, saved
>>> and exited and after that x220 = BRICKED.
>>> I tried every typical troubleshooting/workaround (Removing as much HW as
>>> possible, unplug BIOS battery for hours, etc), nothing worked.
>>> x220 BIOS never booted again and the machine was in a constant boot
>>> loop. Don't know why/how this happened in the first place, but since it is
>>> a custom BIOS and it is very hard to reach the developer, I knew I could
>>> never get it to work without an intrusive method...
>>> *2) Coreboot as Salvation:*
>>> I started to look for alternatives, and luckily, Coreboot supports x220
>>> since a couple of months ago :)
>>> After dealing with all the learning curve to understand the minimal
>>> requirements to compile and install Coreboot (tricky part is basically the
>>> need for HW flashing) I managed to get a working BIOS and x220 is now
>>> (almost 100%) operational :)
>>> I've read and used the blobs from the "damaged" custom BIOS. I'm not
>>> sure if this can affect the functionality of Coreboot. Apparently, it does
>>> *(Let me know if anyone of you need details/help about/with the HW
>>> flashing in this type of chip (MX25L6406E/MX25L6408E)).*
>>> *3) Coreboot rocks but... Current Open issues:*
>>> I decided to use coreboot-4.4 release instead of git-master.
>>> As payload I'm using SeaBIOS (booting Archlinux with Syslinux as
>>> *3.1) RAM speed:*
>>> I've 2 x 8GB DRR3-1866MHz installed. The 16GB are detected but the speed
>>> reported is just 667MHz.
>>> With the official BIOS, the max speed was 1333Mhz. Don't know how
>>> Coreboot is handling this subject in this particular main-board...
>>> DDR timings are a little bit confusing to me, I guess...
>>> Before, with dmidecode -t 17 the speed was 1333Mhz and now it is just
>>> This 667MHz speed I get with coreboot is 2x667=1333Mhz or in reality is
>>> In "northbridge/intel/sandybridge/raminit.c" we can see the following
>>> /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make
>>> * we cap it if we have faster DIMMs.
>>> * Then, align it to the closest JEDEC standard frequency */
>>> *=> So, if I'm understanding it correctly, current 667 Mhz is not the
>>> maximum *
>>> *speed supported.Any idea on how I can get higher speeds?*
>>> *3.2) TP-SMAPI: *
>>> Looks like tp-smapi is not available using Coreboot. It was OK with the
>>> official and custom BIOS before.
>>> From what I've read, this is not a Coreboot limitation... Not sure if
>>> the blobs/EC are not ok for tp-smapi now...
>>> I use tp-smapi for battery threshold, etc. TLP
>>> <http://linrunner.de/en/tlp/tlp.html>also uses tp-smapi. So it is kinda
>>> of important to me.
>>> *=> Anyone using tp-smapi with no problems out there?*
>>> *3.3) Config files:*
>>> coreboot - http://pastebin.com/9ymtxLBW
>>> seabios - http://pastebin.com/rUU7ajRH
>>> cmos.default - http://pastebin.com/Pm5vS15R
>>> Thanks in advance, guys.
>>> All the best \o
>>> coreboot mailing list: coreboot at coreboot.org
> Cumprimentos / Best Regards
> Nuno Moreira
Cumprimentos / Best Regards
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