[coreboot] Need a bigger CBFS size. What's a save value?
dave at 661.org
Tue May 24 10:12:47 CEST 2016
On Tue, 24 May 2016, David Griffith wrote:
> On Mon, 23 May 2016, David Griffith wrote:
>> I'm experimenting with a Thinkpad T60p, specifically getting something
>> working that includes PXE and secondary payloads. Apparently the default
>> CBFS size of 0x40000 is too small because the build process complains it
>> can't add ipxe.rom and guesses that there's no room. Just now I tried
>> specifying a size of 0x200000, thinking that would work because I have a
>> two megabyte SPI flash chip. I went through the procedures on
>> https://www.coreboot.org/Board:lenovo/t60 and
>> https://www.coreboot.org/Board:lenovo/x60/Installation which led to a T60p
>> that shows a black screen and is non-responsive. So, I guess that was a
>> wrong value.
>> So, what's a safe value for the CBFS size that will allow me to add PXE and
>> some other secondary payloads?
> I think my problem wasn't really with the CBFS size, but some apparently
> incorrect advice I got from the IRC channel. I was told that if I clip the
> SPI flash chip to a Beaglebone Black and flash that way then I don't need to
> do these commands prior to flashing (see
> dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) -
> 0x10000] count=64k
> dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) -
> 0x20000] count=64k conv=notrunc
> After trying various sizes of CBFS, pulling the nvram battery, and trying the
> dd switcheroo on a lark, I discovered that I /do/ need to do the switcheroo.
> I tried and failed to flash the SPI chip from the T60p itself, first setting
> BUCTS to 1. After I pulled the nvram battery, BUCTS reported as being 0.
Now it looks like that switcheroo wasn't necessary after all after BUCTS
went back to 0.
dave at 661.org
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