[coreboot] bootfail on my Mohon Peak CRB.

[WANG FEI]

It's great to hear this! Thanks sharing the knowledge with coreboot
community, enjoy your coreboot/FSP journey.

On Tue, May 17, 2016 at 2:39 AM, 김유석 <poplinux0 at gmail.com> wrote:

> Dear Sir.
>
> Thank's your advise.
>
> I was solved this issue.
>
> The cause was "Image size".
>
> My spi flash is have a 16MByte size. and coreboot.rom's size is a 2MByte.
>
> And I was write from 0x00. But x86 is must write from bottom. I guess.
>
>
> *For example*
>
> case 1.
>   coreboot image : 2MByte
>   flash storage : 16MByte
>
>   You must write start address is 0x00E00000(offset 14MByte)
>
> case 2.
>   coreboot image : 8MByte
>   flash storage : 16MByte
>
>   You must write start address is 0x00800000(offset 8MByte)
>
> case 3.
>   coreboot image : 16MByte
>   flash storage : 16MByte
>
>   You must write start address is 0x00000000(offset 0MByte)
>
>
> This time, coreboot work is very fine.
>
> Thank you.
>
> 2016-02-04 오후 11:02에 WANG FEI 이(가) 쓴 글:
>
> *RANGELEY_POSTGOLD4_FSP_004_20150924.fd is the FSP binary, you can rename
> it to FvFsp.bin and placed it to the path defined in coreboot, ie, *
> `../intel/fsp/rangeley/Fv*, to generate coreboot image.*
>
> On Thu, Feb 4, 2016 at 5:19 AM, 김유석 <poplinux0 at gmail.com> wrote:
>
>> Dear Martin.
>>
>> Thank's your advise.
>>
>> I'm use the serial consol port. but can't see any message.
>>
>> Thank you.
>>
>> 2016-02-02 오후 9:18에 Martin Roth 이(가) 쓴 글:
>>
>> You might try a different video card. There's an issue in the video bios
>> of the aspeed card that came with the mohon peak.
>>
>> martin
>> On Tue, Feb 2, 2016 at 00:41 김유석 <poplinux0 at gmail.com> wrote:
>>
>>> Dear sir.
>>>
>>> My ENV is see below.
>>>
>>>   *EVB : Intel rangeley Mohon Peak CRB*
>>>
>>>
>>> This time, I was download the coreboot from git.
>>>
>>>   poplinux at raw work $ > git clone
>>> http://review.coreboot.org/coreboot.git ./
>>>   poplinux at raw work $ > cd coreboot
>>>   poplinux at raw coreboot $ > git submodule update --init --checkout
>>>
>>> Next, *run make menuconfig* and set-up to mohon peak CRB and save & exit
>>>
>>>  * Mainboa**rd*
>>>        Mainboard vendor (*Intel*)  --->
>>>        Mainboard model (*Mohon Peak CRB*)  --->
>>>    [ ] Configure defaults for the Intel FSP package
>>>        ROM chip size (2048 KB (2 MB))  --->
>>>    (0x00200000) Size of CBFS filesystem in ROM
>>>    ()  fmap description file in fmd format
>>>
>>> Next, I'm try to build core boot.
>>>
>>>   poplinux at raw coreboot $ > make
>>>     GEN        generated/bootblock.ld
>>>     CP         bootblock/arch/x86/bootblock.ld
>>>     LINK       cbfs/fallback/bootblock.debug
>>>     OBJCOPY    cbfs/fallback/bootblock.elf
>>>     OBJCOPY    bootblock.raw.bin
>>>     Checking out SeaBIOS revision
>>> 01a84bea2d28a19d2405c1ecac4bdef17683cc0c
>>> Switched to branch 'master'
>>>
>>>   Performing operation on 'COREBOOT' region...
>>>   Name                           Offset     Type         Size
>>>   cbfs master header             0x0        cbfs header  32
>>>   fallback/romstage              0x80       stage        22684
>>>   cpu_microcode_blob.bin         0x5980     microcode    0
>>>   config                         0x5a00     raw          127
>>>   revision                       0x5ac0     raw          570
>>>   cmos_layout.bin                0x5d40     cmos_layout  1316
>>>   fallback/dsdt.aml              0x62c0     raw          7952
>>>   payload_config                 0x8240     raw          1574
>>>   payload_revision               0x88c0     raw          237
>>>   (empty)                        0x8a00     null         29848
>>>   mrc.cache                      0xfec0     mrc_cache    65536
>>>   fallback/ramstage              0x1ff00    stage        46922
>>>   fallback/payload               0x2b6c0    payload      61122
>>>   (empty)                        0x3a5c0    null         1856216
>>>   bootblock                      0x1ff8c0   bootblock    1528
>>>
>>> Finally, I'm got a coreboot image.
>>>
>>>
>>>   poplinux at raw build $ > ls build/coreboot.rom
>>>   build/coreboot.rom
>>>   poplinux at raw build $ > ./build/cbfstool build/coreboot.rom print
>>>   Performing operation on 'COREBOOT' region...
>>>   Name                           Offset     Type         Size
>>>   cbfs master header             0x0        cbfs header  32
>>>   fallback/romstage              0x80       stage        22684
>>>   cpu_microcode_blob.bin         0x5980     microcode    0
>>>   config                         0x5a00     raw          127
>>>   revision                       0x5ac0     raw          570
>>>   cmos_layout.bin                0x5d40     cmos_layout  1316
>>>   fallback/dsdt.aml              0x62c0     raw          7952
>>>   payload_config                 0x8240     raw          1574
>>>   payload_revision               0x88c0     raw          237
>>>   (empty)                        0x8a00     null         29848
>>>   mrc.cache                      0xfec0     mrc_cache    65536
>>>   fallback/ramstage              0x1ff00    stage        46922
>>>   fallback/payload               0x2b6c0    payload      61122
>>>   (empty)                        0x3a5c0    null         1856216
>>>   bootblock                      0x1ff8c0   bootblock    1528
>>>
>>>
>>> And I'm write image to my EVB using *ALL-100 Gang-writ**er*.
>>> spi flash's write *start address is set 0x00000000*. write it success.
>>>
>>> And I'm attach the flash memory to my EVB.
>>>
>>> And power-up the my EVB. But can't see any message on my monitor and
>>> serial port both.
>>>
>>>
>>> *Why did not display any message? *
>>> *A**nd could you support correct configuration file for my EVB?*
>>>
>>> Thank you.
>>>
>>>
>>>
>>>
>>>
>>>
>>> --
>>> coreboot mailing list: <coreboot at coreboot.org>coreboot at coreboot.org
>>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>
>
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