[coreboot] Microcode problem with Braswell CPU

Alexander Böcken Alexander.Boecken at junger-audio.com
Mon May 2 08:28:12 CEST 2016

Hello Zoran,

I really appreciate your help. I was able to resolve the problem on late Friday. I cannot exactly tell what the reason was, however, I set up a fresh install of coreboot, just using my old .config and microcode. Then I saw that the board gets past the microcode update. I must have introduced a bug somewhere... sorry, for the noise...

Now the board stops at TempRamInit in FSP. I'm already using the FSP for Braswell from the Intel link you referenced. The function does not return, but the board shows me post code 0x52. I'm pretty sure the post code comes from FSP because I temporarily redirected all post codes to port 0x84 in the coreboot configuration.

From src/drivers/intel/fsp1_1/cache_as_ram.inc I see that TempRamInit gets a pointer to CAR_init_params which is generated from .config. Those values seem okay.

#define CONFIG_ROM_SIZE               0x200000

Has anyone any experiences with FSP post codes? I can't find any documentation about that.

Thank you,

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