[coreboot] GSoC proposal: Better support for RISC-V systems

Jonathan Neuschäfer j.neuschaefer at gmx.net
Fri Mar 25 17:21:15 CET 2016


On Fri, Mar 25, 2016 at 12:23:19PM +0100, Paul Menzel wrote:
> Dear Jonathan,
> 
> 
> Am Freitag, den 25.03.2016, 04:38 +0100 schrieb Jonathan Neuschäfer:
> 
> > Below is a link to my GSoC project proposal draft[1]. In essence it's
> > about porting coreboot to a non-emulated board with a RISC-V CPU. If you
> > have any comments, please go ahead and add them to the document.
> 
> thank you very much for your promising proposal!

Thanks for taking a look :-)

> > The exact RISC-V board is not yet decided, but I'll fix that as soon as
> > I can.
> 
> What alternatives are there?

I've discussed this some more with Ron, and it will be an untethered
lowRISC[1] ("untethered" meaning that it doesn't use the Host-Target
Interface which is a bridge and abstraction layer for I/O) on a Nexys 4
board by Diligence[2], which has 128MB of RAM.

> > Also, I'm not sure about the timeline. It currently weighs heavily on
> > the first half. Maybe I'm not giving the individual subtasks enough
> > time; maybe I have not listed enough subtasks to fill the three months
> > time frame.
> 
> Looking at it, I’d say, two weeks for implementing RAM initialization
> is a bit short. But I have no idea, if it compares to current x86
> initialization or is more like in the old days.
> 
> What tasks would there be, when – as you noted in your proposal – the
> development does not arrive in time or there are other problems?

I have no good answer to that. I have now changed the first two weeks to
be about getting coreboot (+Linux) to run in a Emulator, but that
certainly can't fill the whole three months.

> If I am not mistaken, you mentioned, you have some Intel GM45 Dell
> laptop with DDR2 memory. Could (start) implementing support for that be
> a backup task?

Yes, I have that laptop, and I will probably try to port it in the
future, but I'm not sure how well it fits in the context of GSoC, given
that I haven't written a proposal and timeline.


Jonathan


[1]: http://www.lowrisc.org/docs/untether-v0.2/
[2]: http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/
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