[coreboot] GSoC proposal: Better support for RISC-V systems

[Jonathan Neuschäfer]

Hi everyone,

Below is a link to my GSoC project proposal draft[1]. In essence it's
about porting coreboot to a non-emulated board with a RISC-V CPU. If you
have any comments, please go ahead and add them to the document.

The exact RISC-V board is not yet decided, but I'll fix that as soon as
I can.

Also, I'm not sure about the timeline. It currently weighs heavily on
the first half. Maybe I'm not giving the individual subtasks enough
time; maybe I have not listed enough subtasks to fill the three months
time frame.


Jonathan

[1]: https://docs.google.com/document/d/1Ex1rP7Y9kX4y5TQCx28uZyqx8iSgih_JyVGnM3fltL8/edit?usp=sharing
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