[coreboot] [GSoC] Good RISC-V support — Questions

[Jonathan Neuschäfer]

Hello,

I'm Jonathan Neuschäfer, a student from Aachen, Germany, and I'm
interested in participating in coreboot's GSoC.

I have some questions about the "coreboot on the open source Berkeley
RISC V processor"[1] project:

- The project page says an FPGA board with a RISC-V soft-core can be
  provided to the student. Does this board (or rather: the programmed
  HDL code) rely on the Host-Target Interface (HTIF)?

  In the long run, we should (also) target "untethered"[2] boards, IMHO,
  simply because they run without the help of another computer.

- Does the board (and the HDL code) have a memory-mapped SPI flash?

  I saw that the untethered lowRISC only has a 64kB boot ROM and an SD
  card slot[3], which would require some form of early block device
  support, as outlined in [4] (although a simple SD driver shouldn't be
  a terrible amount of code).

- Does the board have a RAM controller that needs to be trained?

- Does the board have removable RAM? How is its presence and size
  detected?

- Does the board have a 32- or 64-bit core?


Cheers,
Jonathan


[1]: https://www.coreboot.org/Project_Ideas#coreboot_on_the_open_source_Berkeley_RISC_V_processor
[2]: http://www.lowrisc.org/docs/untether-v0.2/
[3]: http://www.lowrisc.org/docs/untether-v0.2/bootload/
[4]: https://www.coreboot.org/Project_Ideas#Infrastructure_for_accessing_block_devices
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