[coreboot] Porting coreboot to the Asus P5G41T-M LX motherboard

[Renze Nicolai]

Hi Martin,

I added back that function and tried changing / adding some other stuff
and guess what? Serial console works! Thank you for pointing in the
right direction.

Now the next problem: this motherboard uses an Intel X4X northbridge
with DDR3 RAM.

This is the serial console output:
=======================================================================
Setting up RAM controller.
Dimms per channel: 1
2 CPU cores
Capable of DDR2 of 667 MHz or lower
fefffac0: 92 10 0b 02 02 11 00 09 03 52 01 08 0c 00 3c
00  .........R....<.
fefffad0: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01  ixi0i.
.p.<<....
fefffae0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00  ................
fefffaf0: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 01
01  ................
fefffd48: 92 10 0b 02 02 11 00 09 03 52 01 08 0c 00 3c
00  .........R....<.
fefffd58: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01  ixi0i.
.p.<<....
fefffd68: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00  ................
fefffd78: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 01
01  ................
16DS not supported
=======================================================================
https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx/blob/maste
r/serial_log

The code for the Intel X4X northbridge has this not-so-nice line in it:
"// FIXME Add: raminit_ddr3(&s);" which does not suggest anything
good...

Should I start a new thread about DDR3 support for the Intel G41
northbridge?

Greetings,
Renze

On Mon, 2016-03-21 at 14:48 -0600, Martin Roth wrote:
> Ok, looking at the differences between your code ant the GA-G41M
> code, I think you might want to add back in the ich7_enable_lpc()
> function (or something equivalent) .  My guess is that you're not
> sending the necessary IO ports out to LPC.
> 
> Martin
> 
> On Mon, Mar 21, 2016 at 2:25 PM, Renze Nicolai <renze at rnplus.nl>
> wrote:
> > Hi Martin,
> > 
> > Autoport wasn't much use to me since it didn't recognize anything.
> > However it left behind all kinds of logs like the full lspci output
> > and
> > stuff like that -> that's why I shared it.
> > 
> > https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx/blob/m
> > aste
> > r/superiodump
> > 
> > https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx/blob/m
> > aste
> > r/superioextradump
> > 
> > This is the output of superiotool using the OEM BIOS.
> > 
> > The SIO is configured for 0x2E.
> > 
> > Greetings,
> > Renze
> > 
> > On Mon, 2016-03-21 at 13:47 -0600, Martin Roth wrote:
> > > Hi Renze,
> > >   I haven't used Autoport, so I can't help much with that -
> > looking
> > > at the output, I'm not sure this chipset is supported.
> > >
> > > On the console:
> > > Have you run superiotool on your platform with the OEM BIOS?  Can
> > we
> > > get the output from that?  Is your SIO configured for IO address
> > 0x2E
> > > or 0x4E?
> > >
> > > The hang looks unrelated to the console - It looks like you're
> > > failing in memory configuration, so I'd keep adding post codes to
> > see
> > > if you can track down where the actual failure is.  This will
> > > probably become plain once you get the console working though.
> > >
> > > Martin
> > >
> > >
> > > On Fri, Mar 18, 2016 at 4:45 PM, Renze Nicolai <renze at rnplus.nl>
> > > wrote:
> > > > Hello everyone,
> > > >
> > > > I am trying to port coreboot to the Asus P5G41T-M LX
> > motherboard
> > > > but I
> > > > got stuck.
> > > >
> > > > This motherboard has:
> > > >  - Northbridge: Intel G41
> > > >  - Southbridge: ICH7
> > > >  - Super IO: w83627dhg
> > > >
> > > > I used the Gigabye GA-G41M-ES2L code as base since I think it
> > has
> > > > the
> > > > same north- and southbridge. That motherboard has a different
> > Super
> > > > IO
> > > > chip though.
> > > >
> > > > I tried to make the devicetree.cb file valid and I replaced the
> > > > superio
> > > > code in romstage.c with code for the superIO chip on my board.
> > I
> > > > also
> > > > tried to set the correct values in the init code for the
> > superio
> > > > chip
> > > > (irq routing etc).
> > > >
> > > > In romstage.c I added some post codes. The motherboard gets to
> > > > postcode
> > > > 0xA6 and then stops.
> > > >
> > > > Serial output is not working (cable / connection has been
> > tested
> > > > from
> > > > within Linux). Terminal is connected at 115200 baud. No data is
> > > > received.
> > > >
> > > > What I have so far:
> > > > https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx
> > > >
> > > > Logs / info about the board (generated by autoport):
> > > > https://github.com/rnplus/test-coreboot-for-asus-p5g41t-m-lx/tr
> > ee/m
> > > > aste
> > > > r/autoport_logs
> > > >
> > > >
> > > > It would be nice if someone could point me in the right
> > direction
> > > > as to
> > > > what to do next.
> > > >
> > > > Thank you!
> > > >
> > > > Greetings,
> > > > Renze Nicolai
> > > >
> > > > --
> > > > coreboot mailing list: coreboot at coreboot.org
> > > > https://www.coreboot.org/mailman/listinfo/coreboot
> > 
> > --
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> > 
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