[coreboot] Discussion about dynamic PCI MMIO size on x86

[Kyösti Mälkki]

On Mon, Jun 6, 2016 at 10:36 PM, ron minnich <rminnich at gmail.com> wrote:
> I'm getting the sense here that reasonably modern CPUs can easily handle the
> 2G hole. From what I've seen, it would not cause trouble for older CPUs
> because they're most likely to be in small systems that are not likely to
> have more than 2G memory anyway (I'm thinking of the vortex).
>

Not that I would particularly care, but was i945 able to reclaim
memory from below 4GiB to above 4GiB? There used to be a fair amount
of Lenovo T60/X60(s) users.

Additionally, early Atom (model_106cx) might have 32-bit physical
address space only without PAE.

Kyösti

> The 2G hole seems like a reasonable way go to.
>
> ron
>
> On Mon, Jun 6, 2016 at 1:01 AM Gerd Hoffmann <kraxel at redhat.com> wrote:
>>
>>   Hi,
>>
>> > I think one can go with 2GB MMIO hole.
>>
>> Agreeing here.  We have PAE.  Non-ancient 32bit kernels should support
>> and use it, for both security reasons (nox support requires PAE page
>> table format) and accessing physical address space above 4G.
>>
>> > The PCIe > 4GB is a question, I don't
>> > think Windows have good support for this.
>>
>> Depends on the version.  Recent windows versions have no problems
>> handling it.  WinXP throws a BSOD though in case it finds a 64bit mmio
>> window described in \_SB.PCI0._CRS ...
>>
>> cheers,
>>   Gerd
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> https://www.coreboot.org/mailman/listinfo/coreboot
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot