[coreboot] Microcode problem with Braswell CPU

[Zoran Stojsavljevic]

Hello Alex,

It is awhile... Opportunity just did struck (suddenly/plotzlich), so I am
back!

While lurking around in Coreboot, trying to solve some "Mystery of digital
Orga.ni.sms", I ran into very interesting file:
./src/include/console/post_codes.h

Coreboot tree I am using: [zoran at localhost coreboot-09.06.2016]$ git
describe<CR>
4.4-455-g538b324

Maybe, it is worth looking into it. You tell us?

Zoran

On Tue, May 3, 2016 at 10:28 AM, Alexander Böcken <
Alexander.Boecken at junger-audio.com> wrote:

> Hello Zoran,
>
> again, thanks for your clues to this problem. I don't think post code 0x52
> is about memory configuration. The post code appears when I call
> TempRamInit which is supposed to enable Cache-as-RAM. Real memory is
> initialized at a later call to FspMemoryInit. coreboot supplies the
> location of the microcode and a cachable region to TempRamInit.
> Additionally, there are some settings that can be applied to the FSP image
> with Intel's Binary Configuration Tool. I don't know if these are used
> during TempRamInit, but I'll try and fiddle around with them.
>
> I agree, it would be helpful to have a list of post codes that can be
> output by FSP. Otherwise it's all speculation as what is wrong.
>
> Regards,
> Alex
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20160725/8d21e34c/attachment.html>