[coreboot] how to route IRQ4 (COM1) on LPC bus for bayleybay_fsp
adurbin at google.com
Fri Jan 15 20:49:31 CET 2016
On Fri, Jan 15, 2016 at 1:44 PM, benoit <benoit.sansoni at gmail.com> wrote:
> As explained in my post, I am not using the UART located in the Baytrail
> I used an SIO for serial line connected to the LPC bus.
> So to have the IRQs of these serial lines, I obviuosly need to SERIRQ.
> The IRQEN is only for the COM1 located in the SOC.
I missed that part about the SIO. In the past on a bay trail project
we couldn't use SERIRQ because the LPC device and bay trail didn't
support the same SERIRQ frame sequence -- thus badness all around.
Have scoped the SERIRQ lines at all? Maybe the LPC device isn't
asserting? Or maybe SERIRQ isn't running at all.
> Thanks for your help
> On 14/01/2016 23:09, Aaron Durbin wrote:
>> On Tue, Jan 12, 2016 at 2:32 PM, benoit <benoit.sansoni at gmail.com> wrote:
>>> Hi all,
>>> I am currently running coreboot + fsp on a E3837 cpu based platform.
>>> My platform has serial line in a LPC device.
>>> Firstly, I activated the SERIRQ in continous mode.
>> SERIRQ has nothing to do w/ COM1. SERIRQ is pulled in on LPC.
>>> Nevertheless under operating system, the IRQ4 for COM1 is not available.
>> IRQEN (IRQE)—Offset 88h bit 4 indicates UART IRQ4 Enable. The
>> datasheet says RO, but you could double check that it's RW. That sit
>> behind the ILB_BASE_ADDRESS.
>> In the datasheet it's section 34.3.53.
>>> I checked out the file src/mainboard/intel/bayleybay_fsp/irqtable.h
>>> And I saw that for the LPC interface :
>>> PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
>>> #define PIRQ_PIC_ROUTES \
>>> PIRQ_PIC(A, 4), \
>>> PIRQ_PIC(B, 5), \
>>> PIRQ_PIC(C, 7), \
>>> PIRQ_PIC(D, 10), \
>>> PIRQ_PIC(E, 11), \
>>> PIRQ_PIC(F, 12), \
>>> PIRQ_PIC(G, 14), \
>>> PIRQ_PIC(H, 15)
>>> I know that this configuration is available from the ILB_BASE_ADDRESS
>>> But I don't really understand, how to route the IRQ4 from LPC dev.
>>> Is someone can explain to me how to do it properly?
>>> Many thanks in advance
>>> coreboot mailing list: coreboot at coreboot.org
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