[coreboot] Minnowmax: Has anyone used the XDP debug port with coreboot?

[Ben Gardner]

Brett,

Thanks for your input.
Using the SLIM TXE binary did the trick and the Intel System Debugger
now connects to the target without complaint.

Ben

On Thu, Dec 17, 2015 at 2:23 PM, Testerman, Brett (US COM)
<Brett.Testerman at cobham.com> wrote:
> Ben,
>
> You are fighting all the things I had to go through 5 months ago. Not fun. Learned the hard way things like the first steppings of the processor would boot in non-descriptor mode the later ones will not. Even the docs state it one way then correct themselves a few sentences later. And that the processor will boot without a TXE image but like I said before, XDP is disabled. And good luck getting information on writing a SPI driver. The register map is there but nothing on how to use it. Closest equivalent I could find was a PXA270 which is an ARM chip but they obviously reused the IP for the silicon.
>
> We are an embedded product so things like Secure Boot does nothing but get in our way. Was finally able to get it down to just loading the 'SLIM' TXE but making no other changes. Pretty much just zeroed all the TXE setting in the FITC tool for things like the UUID and ODM ID. I did not have to configure any hash's nor do I have to issue any FMI commands. Like you say, by the time you could issue a command coreboot has long since completed. I use an Asset XDP debugger and it catches a power cycle perfectly, halting the CPU as it is about to fetch the reset vector.
>
> I didn't do the hardware design so it would take me quite a while to figure out which GPIO get mapped to the XDP port, especially since they go through a bunch of muxes. If you had something specific I could look early next week as I am out tomorrow. I know the hardware guy did try to follow all the Intel recommendations for the Hooks and such.
>
> We did not make any changes to the GPIO settings the Coreboot defaults to. We do that in the custom payload we load.
>
> Brett
>
>
>
>
>
> -----Original Message-----
> From: Ben Gardner [mailto:gardner.ben at gmail.com]
> Sent: Thursday, December 17, 2015 10:30 AM
> To: Testerman, Brett (US COM)
> Cc: coreboot
> Subject: Re: [coreboot] Minnowmax: Has anyone used the XDP debug port with coreboot?
>
> ** Please note that the Sender of this email is from outside the Cobham NA IT Hub **
>
> Hi Brett,
>
> If you don't mind, I have a few more questions about your setup.
>
> On Thu, Dec 17, 2015 at 10:25 AM, Testerman, Brett (US COM) <Brett.Testerman at cobham.com> wrote:
>> I have a custom E38xx design (Baytrail) that I ported Coreboot on to.
>> XDP works fine but you must install the TXE image in the boot flash
>> else the port is locked out.
>
> We don't need secure boot, so we are chose the 'SLIM' TXE image.
> Did you have to do anything to configure the TXE image, like setting FUSE_FILE_OEM_KEY_HASH_1?
>
> The Intel System Debugger indicates that the "JTAG connection was established but the target appears to have security-restricted JTAG.
> Please try disabling JTAG security in the platform firmware."
> (That was with FSP Gold v3. I haven't yet tested with FSP Gold v4. The XDP hardware is at another location, so testing is a bit difficult.)
>
> Out Intel rep says that we have to send the "Set Debug State" FMI command to the TXE engine to enable debug.
> The problem I ran into with that is that the FspInitEntry (Goldv4) call hides the TXE PCI device (1a.0) and it doesn't seem like I can send a FMI command without RAM first being initialized.
>
> Does any of that sound familiar? Or did it "just work" for your board?
> I would expect it to "just work" if secure boot was disabled.
>
> Last question about your gpio.c file:
> It looks like GPIO_S5[22-30] are used for XDP.
> Minnowmax has GPIO_S5[22] as GPIO_NC and GPIO_S5[23-30] set as GPIO_FUNC(0, PULL_UP, 20K).
>
> Is that how you configured the XDP-related pins?
> If not, would you mind sending you gpio.c file so I can compare?
>
> Thanks,
> Ben
>