[coreboot] Dealing with PCI reset
paulepanter at users.sourceforge.net
Sun Dec 18 23:32:02 CET 2016
Thank you for your reply.
Am Sonntag, den 11.12.2016, 15:54 -0600 schrieb Timothy Pearson:
> > Several devices using the Intel 945 chipset copied code for PCI reset,
> > costing 200 ms of boot time.
> > ```
> > /* Force PCIRST# */
> > pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
> > udelay(200 * 1000);
> > pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
> > ```
> > The change-set Ia37d9f0ecf5655531616edb20b53757d5d47b42f  removes
> > that code from the Lenovo X60.
> > That code was added for some crypto card on a Roda device.
> > My question is, if removing that code is fine, or if it should be left
> > in and be made configurable (Kconfig/NVRAM)?
> > Are there often cases where there are extensions card with problems,
> > that need such a PCI reset?
> We have run into this issue on the KGPE-D16 and LSI SAS controllers.
> However, in this case it's not so much the reset itself as it is the
> time it takes for the card to start up and become ready for PCI scan.
> We handled this with a devicetree.cb option to set a delay between reset
> and PCI scan. Perhaps something similar could be used in this instance?
I guess you are referring to the following line in
register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured
This option is only available for that particular southbridge, AMD
In the Lenovo X60 case, it’d probably would be better to have it as a
run time option in NVRAM, so that it can be configured depending if
such a problematic card is used or not.
Would it be feasible to implement something like that in `src/device`,
so that all devices can use it?
Or is that overkill, and such pluggable(?), that means external, cards
are rare, and the code should just be removed for the Lenovo X60?
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