[coreboot] xHCI support for x86
jwerner at chromium.org
Fri Dec 2 21:49:23 CET 2016
> Do i need to flush cache if event and command rings are located in "normal"
All Intel chipsets I know of support full cache snooping for the
integrated XHCI controller, so you shouldn't need any cache
management. Or are you trying to use an external (e.g. PCIe) XHCI
controller? In that case I think(?) you should still be able to
configure it to cache snoop, but I'm not really an expert in x86
> I use a custom allocator and for now it is not possible to allocate memory as "uncachable"
If your controller really can't cache snoop, then this is the only
supported mechanism to deal with it, sorry. You should be able to set
aside a separate memory region and configure it as uncacheable through
MTRRs or something. (Standard coreboot/libpayload does this by
configuring the memory region in coreboot and then informing
libpayload of it via the LB_TAB_DMA coreboot table entry.
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