[coreboot] coreboot 4.4 release coming soon
Paul Kocialkowski
contact at paulk.fr
Fri Apr 22 15:36:05 CEST 2016
Here is a status report for the chromebooks I'm using:
* veyron_speedy
Boots fine with today's HEAD on a standard use case. However, my particular use
case requires https://review.coreboot.org/#/c/14472/ which is trivial.
* nyan_big
Building with CHROMEOS requires https://review.coreboot.org/#/c/14474/ otherwise
it hangs at bootblock.
Merging the libpayload config before the release would also be nice: https://rev
iew.coreboot.org/#/c/14472/
With those patches applied, the display is mangled on depthcharge as seen on: ht
tp://download.paulk.fr/coreboot/nyan_big/nyan_big-display.jpg
A boot log is attached to this email. It would be useful if someone else could
try and let me know whether they can duplicate the issue.
I'm unsure the issue comes from coreboot, depthcharge or my modifications to
depthcharge and vboot.
The repositories I'm using are:
http://git.code.paulk.fr/gitweb/?p=coreboot.git;a=summary
http://git.code.paulk.fr/gitweb/?p=depthcharge.git;a=summary
http://git.code.paulk.fr/gitweb/?p=vboot.git;a=summary
with branch libreboot-next
Cheers,
--
Paul Kocialkowski, low-level free software developer on embedded devices
Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/
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coreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 bootblock starting...
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 6a52
Ungating power partition 0.
Power gate toggle request accepted.
Ungated power partition 0.
Ungating power partition 15.
Ungated power partition 15.
Ungating power partition 14.
Power gate toggle request accepted.
Ungated power partition 14.
coreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 romstage starting...
Exception handlers installed.
get_sdram_config: RAMCODE=4
Initializing SDRAM of type 2 with 792000KHz
sdram_size_mb: Total SDRAM (MB): 4096
LPAE Translation tables are @ 40000000
Mapping address range [0x00000000:0x80000000) as uncached
Mapping address range [0x40000000:0x40100000) as writeback
Mapping address range [0x80000000:0x00000000) as writeback
Mapping address range [0x90000000:0x90200000) as uncached
Setting address range [0x00000000:0x00100000) as unmapped
CBMEM:
IMD: root @ fdfff000 254 entries.
IMD: root @ fdffec00 62 entries.
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 6b40 size ac26
oreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 ramstage starting...
sdram_size_mb: Total SDRAM (MB): 4096
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
FMAP: Found "FLASH" version 1.1 at 100000.
FMAP: base = 0 size = 400000 #areas = 21
FMAP: area RO_VPD found @ 1f0000 (65536 bytes)
WARNING: RO_VPD is uninitialized or empty.
FMAP: area RW_VPD found @ 2f8000 (32768 bytes)
WARNING: RW_VPD is uninitialized or empty.
Exception handlers installed.
BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 1
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 10761 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 1 run 32806 exit 0
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0
Setting resources...
Root Device assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 50080 exit 0
Enabling resources...
done.
BS: BS_DEV_ENABLE times (us): entry 1 run 2609 exit 1
Initializing devices...
Root Device init ...
USB controller @ 7d000000 set up with UTMI+ PHY
USB controller @ 7d008000 set up with UTMI+ PHY
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
FMAP: area RW_ELOG found @ 27c000 (16384 bytes)
ELOG: FLASH @0x80218440 [SPI 0x0027c000]
ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024
ELOG: Event(17) added with size 13
out: cmd=0x87: 03 32 87 00 00 00 04 00 00 40 00 00
in-header: 03 d5 00 00 04 00 00 00
in-data: 04 20 00 00
out: cmd=0x17: 03 9c 17 00 01 00 14 00 00 00 00 00 04 2e 21 80 05 00 00 00 b1 b0 82 d4 7d 89 20 80
in-header: 03 5d 00 00 10 00 00 00
in-data: 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20
elog_add_boot_reason: Normal mode boot, nothing interesting to log
Root Device init finished in 93480 usecs
CPU_CLUSTER: 0 init ...
Extracted contents:
header: 00 ff ff ff ff ff ff 00
serial number: 06 af 2c 13 00 00 00 00 00 18
version: 01 03
basic params: 80 1d 10 78 0a
chroma info: bb f5 94 55 54 90 27 23 50 54
established: 00 00 00
standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1: 26 1b 56 64 50 00 16 30 30 20 36 00 25 a4 10 00 00 18
descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
descriptor 4: 00 00 00 fe 00 42 31 33 33 58 54 4e 30 31 2e 33 20 0a
extensions: 00
checksum: 4b
Manufacturer: AUO Model 132c Serial Number 0
Made week 0 of 2014
EDID version: 1.3
Digital display
Maximum image size: 29 cm x 16 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4, YCrCb 4:2:2
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 261b5664500016303020360025a410000018
Detailed mode (IN HEX): Clock 69500 KHz, 125 mm x a4 mm
0556 0586 05a6 05ba hborder 0
0300 0303 0309 0316 vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 0000000f0000000000000000000000000020
Manufacturer-specified data, tag 15
Hex of detail: 000000fe0041554f0a202020202020202020
ASCII string: AUO
Hex of detail: 000000fe004231333358544e30312e33200a
ASCII string: B133XTN01.3
Checksum
Checksum: 0x4b (valid)
WARNING: EDID block does NOT fully conform to EDID 1.3.
Missing name descriptor
Missing monitor ranges
tegra_dp_update_config: configuration updated by EDID.
display_startup: backlight vdd setting gpio 000e007a to 1
Mapping address range [0xfe000000:0xfe300000) as writethrough
LCD frame buffer at 4064MiB to 4067MiB
clock_display: PLLD=139000000 ref=12000000, m/n/p/cpcon=3/139/2/3
MODE:1366x768 at 60.008Hz pclk=69500000
update_display_mode: PixelClock=69500000, ShiftClockDiv=1
DP config: cfg_name cfg_value
Lane Count 1
SupportEnhancedFraming Y
Bandwidth 10
bpp 18
EnhancedFraming Y
Scramble_enabled N
LinkBW 10
lane_count 1
activespolarity 0
active_count 37
tu_size 64
active_frac 15
watermark 18
hblank_sym 346
vblank_sym 5169
DP config: cfg_name cfg_value
Lane Count 1
SupportEnhancedFraming Y
Bandwidth 10
bpp 18
EnhancedFraming Y
Scramble_enabled N
LinkBW 10
lane_count 1
activespolarity 0
active_count 37
tu_size 64
active_frac 15
watermark 18
hblank_sym 346
vblank_sym 5169
Fast link trainging succeeded, link bw 10, lane 1
tegra_dc_sor_attach: sor is attached
display_startup: enable panel backlight pwm
display_startup: backlight enable setting gpio 0086003a to 1
display_startup: display init done.
CPU: Tegra124
CPU_CLUSTER: 0 init finished in 546481 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 658619 exit 0
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 1 run 3473 exit 0
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
Writing coreboot table at 0xfdfdb000
0. 0000000080000000-00000000fdfdafff: RAM
1. 00000000fdfdb000-00000000fdffffff: CONFIGURATION TABLES
2. 00000000fe000000-00000000ffffffff: RESERVED
3. 0000000100000000-000000017fffffff: RAM
out: cmd=0x87: 03 72 87 00 00 00 04 00 00 00 00 00
in-header: 03 d5 00 00 04 00 00 00
in-data: 04 20 00 00
Passing 7 GPIOs to payload:
NAME | PORT | POLARITY | VALUE
write protect | 0x00b00089 | low | high
recovery | undefined | high | high
lid | 0x00b3008c | high | undefined
power | 0x00bf0080 | low | undefined
developer | undefined | high | high
EC in RW | 0x006500a4 | high | undefined
reset | 0x00710045 | low | undefined
Reading tristate GPIOs: 0 0 1 1 = 4 (standard base3 number system)
Board TRISTATE ID: 4.
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
Wrote coreboot table at: fdfdb000, 0x2cc bytes, checksum 7d62
coreboot table: 740 bytes.
IMD ROOT 0. fdfff000 00001000
IMD SMALL 1. fdffe000 00001000
CONSOLE 2. fdfde000 00020000
TIME STAMP 3. fdfdd000 00000400
COREBOOT 4. fdfdb000 00002000
IMD small region:
IMD ROOT 0. fdffec00 00000400
BS: BS_WRITE_TABLES times (us): entry 1 run 118071 exit 0
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 117c0 size 1476f
Loading segment from rom address 0x80100000
code (compression=1)
New segment dstaddr 0x83104040 memsize 0x651660 srcaddr 0x80100038 filesize 0x14737
Loading segment from rom address 0x8010001c
Entry Point 0x83104041
Bounce Buffer at fdfa3000, 226432 bytes
Loading Segment: addr: 0x0000000083104040 memsz: 0x0000000000651660 filesz: 0x0000000000014737
lb: [0x0000000080200000, 0x000000008021ba40)
Post relocation: addr: 0x0000000083104040 memsz: 0x0000000000651660 filesz: 0x0000000000014737
using LZMA
[ 0x83104040, 83128f1c, 0x837556a0) <- 80100038
Clearing Segment: addr: 0x0000000083128f1c memsz: 0x000000000062c784
dest 83104040, end 837556a0, bouncebuffer fdfa3000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 120061 exit 0
Jumping to boot code at 83104041(fdfdb000)
CPU0: stack: 4000e000 - 40010000, lowest used address 4000fb58, stack used: 1192 bytes
Starting depthcharge on nyan_big...
The GBB signature is at 0x83004020 and is: 24 47 42 42
vboot handoff pointer is NULL
vboot_init:63 dev 0, rec 0, wp 1, lid 1, oprom 0
Calling VbInit().
VbInit() input flags 0x1264 gbb flags 0x30
cros_ec_init: CrosEC protocol v3 supported (544, 544)
Google ChromeOS EC driver ready, id 'big_v1.1.1807-2252740'
Clearing the recovery request.
VbSharedDataInit, 16384 bytes, header 1096 bytes
VbInit sees recovery request = 0
VbInit now sets shared->recovery_reason = 0
TPM: Call RollbackFirmwareSetup(r0, d0)
TPM: Startup
1.2 TPM (chip type slb9645tt device-id 0x1A)
TPM: command 0x99 returned 0x0
TPM: Asserting physical presence
TPM: command 0x4000000a returned 0x0
TPM: command 0x65 returned 0x0
TPM: Got flags disable=0, deactivated=0, nvlocked=1
TPM: TlclRead(0x1007, 10)
TPM: command 0xcf returned 0x0
TPM: Firmware space sv2 f3 v50001
TPM: SetupTPM() succeeded
TPM: RollbackFirmwareSetup 50001
VbInit() output flags 0xce
VbInit() returning 0x0
Wipe memory regions:
[0x00000080000000, 0x00000081000000)
[0x00000081000200, 0x00000083000000)
[0x000000837556a0, 0x00000087f00000)
[0x00000088000000, 0x000000fdfdb000)
[0x00000100000000, 0x00000180000000)
Work block for LPAE mapping is @ 0x0x83800000
Initializing EHCI USB controller at 0x7d008100.
Initializing EHCI USB controller at 0x7d000100.
Calling VbSelectFirmware().
LoadFirmware started...
Checking key block signature...
- sig_size=1024, expecting 1024 for algorithm 11
Verifying preamble.
- sig_size=512, expecting 512 for algorithm 7
Preamble flags 0x0
FMAP section too small.
VbExHashFirmwareBody() failed for index 0
Checking key block signature...
- sig_size=1024, expecting 1024 for algorithm 11
Verifying preamble.
- sig_size=512, expecting 512 for algorithm 7
Preamble flags 0x0
FMAP section too small.
VbExHashFirmwareBody() failed for index 1
Alas, no good firmware.
VbSelectFirmware returned 65539, Doing a cold reboot.
Exiting depthcharge with code 1 at timestamp: �coreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 bootblock starting...
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 6a52
Ungating power partition 0.
Power gate toggle request accepted.
Ungated power partition 0.
Ungating power partition 15.
Ungated power partition 15.
Ungating power partition 14.
Power gate toggle request accepted.
Ungated power partition 14.
coreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 romstage starting...
Exception handlers installed.
get_sdram_config: RAMCODE=4
Initializing SDRAM of type 2 with 792000KHz
sdram_size_mb: Total SDRAM (MB): 4096
LPAE Translation tables are @ 40000000
Mapping address range [0x00000000:0x80000000) as uncached
Mapping address range [0x40000000:0x40100000) as writeback
Mapping address range [0x80000000:0x00000000) as writeback
Mapping address range [0x90000000:0x90200000) as uncached
Setting address range [0x00000000:0x00100000) as unmapped
CBMEM:
IMD: root @ fdfff000 254 entries.
IMD: root @ fdffec00 62 entries.
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 6b40 size ac26
oreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 ramstage starting...
sdram_size_mb: Total SDRAM (MB): 4096
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
FMAP: Found "FLASH" version 1.1 at 100000.
FMAP: base = 0 size = 400000 #areas = 21
FMAP: area RO_VPD found @ 1f0000 (65536 bytes)
WARNING: RO_VPD is uninitialized or empty.
FMAP: area RW_VPD found @ 2f8000 (32768 bytes)
WARNING: RW_VPD is uninitialized or empty.
Exception handlers installed.
BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 1 run 1 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
Root Device scanning...
root_dev_scan_bus for Root Device
CPU_CLUSTER: 0 enabled
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 10760 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 1 run 32805 exit 1
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0
Setting resources...
Root Device assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 50080 exit 0
Enabling resources...
done.
BS: BS_DEV_ENABLE times (us): entry 0 run 2611 exit 0
Initializing devices...
Root Device init ...
USB controller @ 7d000000 set up with UTMI+ PHY
USB controller @ 7d008000 set up with UTMI+ PHY
SF: Detected W25Q32DW with sector size 0x1000, total 0x400000
FMAP: area RW_ELOG found @ 27c000 (16384 bytes)
ELOG: FLASH @0x80218440 [SPI 0x0027c000]
ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024
ELOG: Event(17) added with size 13
out: cmd=0x87: 03 32 87 00 00 00 04 00 00 40 00 00
in-header: 03 d5 00 00 04 00 00 00
in-data: 04 20 00 00
out: cmd=0x17: 03 cc 17 00 01 00 14 00 00 00 00 00 04 2e 21 80 05 00 00 00 91 a0 82 d4 7d 89 20 80
in-header: 03 ed 00 00 10 00 00 00
in-data: 70 00 19 00 00 00 00 00 00 00 00 00 00 00 00 77
ELOG: Event(A1) added with size 10
elog_add_boot_reason: Logged recovery mode boot, reason: 0x00
Root Device init finished in 100283 usecs
CPU_CLUSTER: 0 init ...
Extracted contents:
header: 00 ff ff ff ff ff ff 00
serial number: 06 af 2c 13 00 00 00 00 00 18
version: 01 03
basic params: 80 1d 10 78 0a
chroma info: bb f5 94 55 54 90 27 23 50 54
established: 00 00 00
standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1: 26 1b 56 64 50 00 16 30 30 20 36 00 25 a4 10 00 00 18
descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
descriptor 4: 00 00 00 fe 00 42 31 33 33 58 54 4e 30 31 2e 33 20 0a
extensions: 00
checksum: 4b
Manufacturer: AUO Model 132c Serial Number 0
Made week 0 of 2014
EDID version: 1.3
Digital display
Maximum image size: 29 cm x 16 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4, YCrCb 4:2:2
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 261b5664500016303020360025a410000018
Detailed mode (IN HEX): Clock 69500 KHz, 125 mm x a4 mm
0556 0586 05a6 05ba hborder 0
0300 0303 0309 0316 vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 0000000f0000000000000000000000000020
Manufacturer-specified data, tag 15
Hex of detail: 000000fe0041554f0a202020202020202020
ASCII string: AUO
Hex of detail: 000000fe004231333358544e30312e33200a
ASCII string: B133XTN01.3
Checksum
Checksum: 0x4b (valid)
WARNING: EDID block does NOT fully conform to EDID 1.3.
Missing name descriptor
Missing monitor ranges
tegra_dp_update_config: configuration updated by EDID.
display_startup: backlight vdd setting gpio 000e007a to 1
Mapping address range [0xfe000000:0xfe300000) as writethrough
LCD frame buffer at 4064MiB to 4067MiB
clock_display: PLLD=139000000 ref=12000000, m/n/p/cpcon=3/139/2/3
MODE:1366x768 at 60.008Hz pclk=69500000
update_display_mode: PixelClock=69500000, ShiftClockDiv=1
DP config: cfg_name cfg_value
Lane Count 1
SupportEnhancedFraming Y
Bandwidth 10
bpp 18
EnhancedFraming Y
Scramble_enabled N
LinkBW 10
lane_count 1
activespolarity 0
active_count 37
tu_size 64
active_frac 15
watermark 18
hblank_sym 346
vblank_sym 5169
DP config: cfg_name cfg_value
Lane Count 1
SupportEnhancedFraming Y
Bandwidth 10
bpp 18
EnhancedFraming Y
Scramble_enabled N
LinkBW 10
lane_count 1
activespolarity 0
active_count 37
tu_size 64
active_frac 15
watermark 18
hblank_sym 346
vblank_sym 5169
Fast link trainging succeeded, link bw 10, lane 1
tegra_dc_sor_attach: sor is attached
display_startup: enable panel backlight pwm
display_startup: backlight enable setting gpio 0086003a to 1
display_startup: display init done.
CPU: Tegra124
CPU_CLUSTER: 0 init finished in 546602 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
BS: BS_DEV_INIT times (us): entry 1 run 665629 exit 0
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 1 run 3473 exit 1
BS: BS_OS_RESUME_CHECK times (us): entry 1 run 0 exit 1
Writing coreboot table at 0xfdfdb000
0. 0000000080000000-00000000fdfdafff: RAM
1. 00000000fdfdb000-00000000fdffffff: CONFIGURATION TABLES
2. 00000000fe000000-00000000ffffffff: RESERVED
3. 0000000100000000-000000017fffffff: RAM
out: cmd=0x87: 03 72 87 00 00 00 04 00 00 00 00 00
in-header: 03 d5 00 00 04 00 00 00
in-data: 04 20 00 00
Passing 7 GPIOs to payload:
NAME | PORT | POLARITY | VALUE
write protect | 0x00b00089 | low | high
recovery | undefined | high | high
lid | 0x00b3008c | high | undefined
power | 0x00bf0080 | low | undefined
developer | undefined | high | high
EC in RW | 0x006500a4 | high | undefined
reset | 0x00710045 | low | undefined
Reading tristate GPIOs: 0 0 1 1 = 4 (standard base3 number system)
Board TRISTATE ID: 4.
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
Wrote coreboot table at: fdfdb000, 0x2cc bytes, checksum 7d62
coreboot table: 740 bytes.
IMD ROOT 0. fdfff000 00001000
IMD SMALL 1. fdffe000 00001000
CONSOLE 2. fdfde000 00020000
TIME STAMP 3. fdfdd000 00000400
COREBOOT 4. fdfdb000 00002000
IMD small region:
IMD ROOT 0. fdffec00 00000400
BS: BS_WRITE_TABLES times (us): entry 0 run 118070 exit 0
CBFS @ 20000 size e0000
CBFS: 'Master Header Locator' located CBFS at [20000:100000)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 117c0 size 1476f
Loading segment from rom address 0x80100000
code (compression=1)
New segment dstaddr 0x83104040 memsize 0x651660 srcaddr 0x80100038 filesize 0x14737
Loading segment from rom address 0x8010001c
Entry Point 0x83104041
Bounce Buffer at fdfa3000, 226432 bytes
Loading Segment: addr: 0x0000000083104040 memsz: 0x0000000000651660 filesz: 0x0000000000014737
lb: [0x0000000080200000, 0x000000008021ba40)
Post relocation: addr: 0x0000000083104040 memsz: 0x0000000000651660 filesz: 0x0000000000014737
using LZMA
[ 0x83104040, 83128f1c, 0x837556a0) <- 80100038
Clearing Segment: addr: 0x0000000083128f1c memsz: 0x000000000062c784
dest 83104040, end 837556a0, bouncebuffer fdfa3000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 120082 exit 1
Jumping to boot code at 83104041(fdfdb000)
CPU0: stack: 4000e000 - 40010000, lowest used address 4000fb58, stack used: 1192 bytes
Starting depthcharge on nyan_big...
The GBB signature is at 0x83004020 and is: 24 47 42 42
vboot handoff pointer is NULL
vboot_init:63 dev 0, rec 0, wp 1, lid 1, oprom 0
Calling VbInit().
VbInit() input flags 0x1264 gbb flags 0x30
cros_ec_init: CrosEC protocol v3 supported (544, 544)
Google ChromeOS EC driver ready, id 'big_v1.1.1807-2252740'
Clearing the recovery request.
VbSharedDataInit, 16384 bytes, header 1096 bytes
VbInit sees recovery request = 25
VbInit now sets shared->recovery_reason = 25
TPM: Call RollbackFirmwareSetup(r25, d0)
TPM: Startup
1.2 TPM (chip type slb9645tt device-id 0x1A)
TPM: command 0x99 returned 0x0
TPM: Asserting physical presence
TPM: command 0x4000000a returned 0x0
TPM: command 0x65 returned 0x0
TPM: Got flags disable=0, deactivated=0, nvlocked=1
TPM: TlclRead(0x1007, 10)
TPM: command 0xcf returned 0x0
TPM: Firmware space sv2 f3 v50001
TPM: SetupTPM() succeeded
TPM: RollbackFirmwareSetup 50001
VbInit() output flags 0xf
VbInit() returning 0x0
Wipe memory regions:
[0x00000080000000, 0x00000081000000)
[0x00000081000200, 0x00000083000000)
[0x000000837556a0, 0x00000087f00000)
[0x00000088000000, 0x000000fdfdb000)
[0x00000100000000, 0x00000180000000)
Work block for LPAE mapping is @ 0x0x83800000
Initializing EHCI USB controller at 0x7d008100.
Initializing EHCI USB controller at 0x7d000100.
Calling VbSelectFirmware().
VbSelectFirmware() detected recovery request
TPM: command 0x14 returned 0x0
TPM: SetTPMBootModeState boot mode PCR0 result 0
TPM: command 0x14 returned 0x0
TPM: SetTPMBootModeState HWID PCR1 result 0
Calling VbSelectAndLoadKernel().
VbEcSoftwareSync(devidx=0)
VbEcSoftwareSync() in recovery; EC-RO
PARAM_LIMIT_POWER not supported by EC.
TPM: TlclRead(0x1008, 13)
TPM: command 0xcf returned 0x0
TPM: command 0x65 returned 0x0
TPM: RollbackKernelRead 10001
VbBootRecovery() start
VbBootRecovery() waiting for a recovery image
VbBootRecovery() attempting to load kernel2
VbTryLoadKernel() start, get_info_flags=0x1
VbTryLoadKernel() found 0 disks
VbSetRecoveryRequest(90)
VbSetRecoveryRequest(0)
backlight_update called but not implemented.
VbBootRecovery() attempting to load kernel2
VbTryLoadKernel() start, get_info_flags=0x1
VbTryLoadKernel() found 0 disks
VbSetRecoveryRequest(90)
VbSetRecoveryRequest(0)
VbBootRecovery() attempting to load kernel2
VbTryLoadKernel() start, get_info_flags=0x1
VbTryLoadKernel() found 0 disks
VbSetRecoveryRequest(90)
VbSetRecoveryRequest(0)
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