[coreboot] Acer Chromebook 15 debug

[John Lewis]

I'm still no further along. On the very first boot after flash I get:

coreboot-5cbe3a8-dirty romstage Thu Sep  3 10:28:23 BST 2015 starting...

PM1_STS:   0010
PM1_EN:    0000
PM1_CNT:   00000000
TCO_STS:   0000 0000
GPE0_STS:  1ef86df0 187d4fdf 0005f240 00010000
GPE0_EN:   00000000 00000000 00000000 00000000
GEN_PMCON: 0200 20a0 1a09
Previous Sleep State: S0
CPU: Intel(R) Core(TM) i3-5005U CPU @ 2.00GHz
CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001d
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 1604 (rev 09) is Broadwell F0
PCH: device id 9cc5 (rev 03) is Broadwell U Base
IGD: device id 1616 (rev 09) is Broadwell U GT2
CPU: frequency set to 2000 MHz
POST: 0x32
SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)
SPD: module type is DDR3
SPD: module part is HMT425S6AFR6A-PB
SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb
SPD: device width 16 bits, bus width 64 bits
SPD: module size is 2048 MB (per channel)
POST: 0x32
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : Waiting for DID BIOS message
ME: HSIO Version            : 8705 (CRC 0xfbc2)
No MRC cache found.
Rebooting with EC in RO mode:
POST: 0x00

Reverting to the previous log on subsequent boots. Note I have also 
built the ROM inside the CrOS SDK.

What should I do now?

See attached changes + config.

-John.
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