[coreboot] Acer Chromebook 15 debug
John Lewis
jlewis at johnlewis.ie
Wed Sep 2 09:45:09 CET 2015
I think I'm going to come at this from a different angle. I'm trying to
do a fresh build and here is what I have so far. What's the best way of
getting around these errors?:
build/lib/cbfs.romstage.o: In function `load_stage_from_cbfs':
/home/dad/coreboot/firmware-yuna-6301.59.B/src/lib/cbfs.c:132: undefined
reference to `rmodule_stage_load_from_cbfs'
build/soc/intel/broadwell/romstage/romstage.romstage.o: In function
`romstage_main':
/home/dad/coreboot/firmware-yuna-6301.59.B/src/soc/intel/broadwell/romstage/romstage.c:75:
undefined reference to `mainboard_pre_console_init'
collect2: error: ld returned 1 exit status
src/arch/x86/Makefile.inc:213: recipe for target
'build/cbfs/fallback/romstage_null.debug' failed
make: *** [build/cbfs/fallback/romstage_null.debug] Error 1
These are the changes I've made so far:
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 0ef12fb..1e058a7 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -161,6 +161,7 @@ void google_chromeec_check_ec_image(int
expected_type)
}
}
+#if CONFIG_CHROMEOS
/* Check for recovery mode and ensure EC is in RO */
void google_chromeec_early_init(void)
{
@@ -169,6 +170,7 @@ void google_chromeec_early_init(void)
google_chromeec_check_ec_image(EC_IMAGE_RO);
}
}
+#endif
void google_chromeec_check_pd_image(int expected_type)
{
@@ -200,6 +202,7 @@ void google_chromeec_check_pd_image(int
expected_type)
}
}
+#if CONFIG_CHROMEOS
/* Check for recovery mode and ensure PD is in RO */
void google_chromeec_early_pd_init(void)
{
@@ -210,6 +213,8 @@ void google_chromeec_early_pd_init(void)
}
#endif
+#endif
+
u16 google_chromeec_get_board_version(void)
{
struct chromeec_command cmd;
diff --git a/src/mainboard/google/auron_yuna/Kconfig
b/src/mainboard/google/auron_yuna/Kconfig
index 2db9689..1e56e0f 100644
--- a/src/mainboard/google/auron_yuna/Kconfig
+++ b/src/mainboard/google/auron_yuna/Kconfig
@@ -12,8 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
- select CHROMEOS
- select CHROMEOS_VBNV_CMOS
select EXTERNAL_MRC_BLOB
select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
diff --git a/src/mainboard/google/auron_yuna/romstage.c
b/src/mainboard/google/auron_yuna/romstage.c
index 705b0af..c1a3916 100644
--- a/src/mainboard/google/auron_yuna/romstage.c
+++ b/src/mainboard/google/auron_yuna/romstage.c
@@ -35,8 +35,10 @@ void mainboard_romstage_entry(struct romstage_params
*rp)
post_code(0x32);
+ #if CONFIG_CHROMEOS
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
+ #endif
/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);
And this is my current .config (minus things which aren't set):
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_ALT_CBFS_LOAD_PAYLOAD=y
CONFIG_COMPILER_GCC=y
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_DYNAMIC_CBMEM=y
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="google/auron_yuna"
CONFIG_MAINBOARD_PART_NUMBER="Auron_Yuna"
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_MAINBOARD_VENDOR="GOOGLE"
CONFIG_MAX_CPUS=8
CONFIG_RAMTOP=0x200000
CONFIG_HEAP_SIZE=0x4000
CONFIG_RAMBASE=0x100000
CONFIG_VGA_BIOS_ID="8086,1616"
CONFIG_STACK_SIZE=0x1000
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_VGA_BIOS=y
CONFIG_CONSOLE_POST=y
CONFIG_DCACHE_RAM_BASE=0xff7c0000
CONFIG_DCACHE_RAM_SIZE=0x10000
CONFIG_SERIAL_CPU_INIT=y
CONFIG_ACPI_SSDTX_NUM=0
CONFIG_VGA_BIOS_FILE="pci8086,0406.rom"
CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_XIP_ROM_SIZE=0x10000
CONFIG_VENDOR_SPECIFIC_OPTIONS=y
CONFIG_BOARD_GOOGLE_AURON_YUNA=y
CONFIG_VBOOT_RAMSTAGE_INDEX=0x2
CONFIG_VBOOT_REFCODE_INDEX=0x3
CONFIG_MAINBOARD_FAMILY="Google_Auron"
CONFIG_BOOT_MEDIA_SPI_BUS=0
CONFIG_MMCONF_SUPPORT_DEFAULT=y
CONFIG_LOGICAL_CPUS=y
CONFIG_IOAPIC=y
CONFIG_SMP=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
CONFIG_USBDEBUG=y
CONFIG_CPU_ADDR_BITS=36
CONFIG_BOARD_ROMSIZE_KB_8192=y
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
CONFIG_COREBOOT_ROMSIZE_KB=8192
CONFIG_ROM_SIZE=0x800000
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_ENCLOSURE_TYPE=0x3
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_MARK_GRAPHICS_MEM_WRCOMB=y
CONFIG_X86_BOOTBLOCK_SIMPLE=y
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
CONFIG_PC80_SYSTEM=y
CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="soc/intel/broadwell/bootblock/systemagent.c"
CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="soc/intel/broadwell/bootblock/pch.c"
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
CONFIG_HPET_ADDRESS=0xfed00000
CONFIG_ID_SECTION_OFFSET=0x80
CONFIG_ARM_BOOTBLOCK_SIMPLE=y
CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/broadwell/bootblock/cpu.c"
CONFIG_CPU_SPECIFIC_OPTIONS=y
CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
CONFIG_SMM_TSEG_SIZE=0
CONFIG_MICROCODE_INCLUDE_PATH="src/soc/intel/broadwell/microcode"
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_MONOTONIC_TIMER_MSR=y
CONFIG_SSE2=y
CONFIG_CACHE_MRC_BIN=y
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
CONFIG_UDELAY_TSC=y
CONFIG_TSC_CONSTANT_RATE=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_CACHE_ROM=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_MODULES=y
CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
CONFIG_PARALLEL_MP=y
CONFIG_BACKUP_DEFAULT_SMM_REGION=y
CONFIG_CACHE_AS_RAM=y
CONFIG_AP_SIPI_VECTOR=0xfffff000
CONFIG_CPU_MICROCODE_IN_CBFS=y
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
CONFIG_CAR_MIGRATION=y
CONFIG_VIDEO_MB=0
CONFIG_CBFS_SIZE=0x100000
CONFIG_CACHE_MRC_SIZE_KB=512
CONFIG_EXTERNAL_MRC_BLOB=y
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
CONFIG_HAVE_MRC=y
CONFIG_MRC_FILE="mrc.bin"
CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE=0x2000
CONFIG_PRE_GRAPHICS_DELAY=0
CONFIG_EHCI_BAR=0xd8000000
CONFIG_EHCI_DEBUG_OFFSET=0xa0
CONFIG_USBDEBUG_DEFAULT_PORT=1
CONFIG_SPI_FLASH=y
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_EC_GOOGLE_CHROMEEC=y
CONFIG_EC_GOOGLE_CHROMEEC_LPC=y
CONFIG_MRC_BIN_ADDRESS=0xfffa0000
CONFIG_SOC_INTEL_BROADWELL=y
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_CACHE_BASE=0xffb00000
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_ALWAYS_LOAD_OPROM=y
CONFIG_PCI=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_AGP_PLUGIN_SUPPORT=y
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCI_BUS_SEGN_BITS=0
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_ELOG=y
CONFIG_ELOG_FLASH_BASE=0
CONFIG_ELOG_AREA_SIZE=0x1000
CONFIG_ELOG_FULL_THRESHOLD=0xC00
CONFIG_ELOG_SHRINK_SIZE=0x400
CONFIG_ELOG_GSMI=y
CONFIG_ELOG_BOOT_COUNT=y
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
CONFIG_DRIVERS_MC146818_RTC=y
CONFIG_DRIVERS_MC146818_CMOS=y
CONFIG_DRIVERS_RTC_HAS_ALTCENTURY=y
CONFIG_SPI_ATOMIC_SEQUENCING=y
CONFIG_SPI_FLASH_MEMORY_MAPPED=y
CONFIG_SPI_FLASH_SMM=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_MMCONF_SUPPORT=y
CONFIG_EARLY_CONSOLE=y
CONFIG_HAVE_USBDEBUG=y
CONFIG_CONSOLE_CBMEM=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0xc00
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
CONFIG_HAVE_UART_IO_MAPPED=y
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_HAVE_HARD_RESET=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_CACHE_ROM_SIZE=0x100000
CONFIG_RELOCATABLE_MODULES=y
CONFIG_RELOCATABLE_RAMSTAGE=y
CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y
CONFIG_HAVE_REFCODE_BLOB=y
CONFIG_REFCODE_BLOB_FILE="refcode.elf"
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_MAX_PIRQ_LINKS=4
CONFIG_GENERATE_ACPI_TABLES=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_PAYLOAD_SEABIOS=y
CONFIG_SEABIOS_MASTER=y
CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf"
CONFIG_COMPRESSED_PAYLOAD_LZMA=y
CONFIG_REG_SCRIPT=y
CONFIG_CHROMEOS_RAMOOPS_DYNAMIC=y
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
CONFIG_MAX_REBOOT_CNT=3
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