[coreboot] Moving forward with armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write

[Paul Kocialkowski]

For nearly a month, a few people (includign myself) have been arguing
over http://review.coreboot.org/#/c/11698/

So far, we've investigated two solutions:
* inline assembly
* __builtin_assume_aligned builtin

Each solution has its pros and cons, I'm not going to move that
discussion here.

However, I would like to suggest another solution: reverting the
toolchain built by crossgcc-arm to GCC 4.9.0, where everything works
fine. That would only be for ARM, since GCC 4.9.0 apparently breaks
RISC-V support and wasn't reported to misbehave on other architectures.

I wish to use the toolchain for rebuilding the cros EC firmware
(especially important for libreboot) and GCC 5.2.0 is causing run-time
errors that are apparently not even of the same nature as the problem
discussed in code review.

Would this be an agreeable solution until everything is sorted out in
gcc upstream?

-- 
Paul Kocialkowski, Replicant developer

Replicant is a fully free Android distribution running on several
devices, a free software mobile operating system putting the emphasis on
freedom and privacy/security.

Website: https://www.replicant.us/
Blog: https://blog.replicant.us/
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