[coreboot] Rebuilding coreboot image generation

[Patrick Georgi]

2015-11-06 6:55 GMT+01:00 Julius Werner <jwerner at chromium.org>:
> HOST_FIRMWARE at 0xff800000 8M {
>         SI_ALL 2M {
>                 SI_DESC 4K
>                 SI_ME 0x1ff000
>         }
>         SI_BIOS {
>                 RW_A 0xf0000 {
>                         VBLOCK_A 64K
>                         RW_MAIN_A
>                         RW_FWID_A 0x40
>                 }
>                 RW_B 0xf0000 {
>                         VBLOCK_B 64K
>                         RW_MAIN_B
>                         RW_FWID_B 0x40
>                 }
>                 RO at 4M {
>                         RO_VPD 16K
>                         FMAP at 0x10000 2K
>                         RO_FRID 0x40
>                         GBB at 0x11000
>                         RO_MAIN 1M
>                 }
>         }
> }
Just wanted to spell out the issues with this approach:
First, it doesn't tell you where to put various build collateral. Is
ramstage.elf to be added to SI_ME?

Second, this requires more or less one such description file per board
and boot method configuration, which is even worse than Alexandru's
concern about having a reenactment of horribly maintained cmos.layout
files (they're "merely" per board, but otherwise stable).


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle