[coreboot] AGESA PI for Olivehill+

[Wolfgang Kamp - datakamp]

Hello Kyösti,

thank you for your help. I have got the DB-FT3b-LC coreboot OSP package and I can see how things work in agesawrapper.c.
My starting point is Olivehill+ and I moved the agesawrapper.c to mainboard directory. Because now the agesawrapper is board specific I think it belongs there as it is in family 14H. And memory down in star topology now works fine in our board. Next problem is how to configure the GFX ports to get DVI and eDP.

Regards,
Wolfgang

-----Ursprüngliche Nachricht-----
Von: coreboot [mailto:coreboot-bounces at coreboot.org] Im Auftrag von Kyösti Mälkki
Gesendet: Mittwoch, 13. Mai 2015 11:27
An: Wim Vervoorn
Cc: Wolfgang Kamp - datakamp; coreboot at coreboot.org
Betreff: Re: [coreboot] AGESA PI for Olivehill+

On ke, 2015-05-13 at 10:18 +0200, Wim Vervoorn wrote:
> Hello Kyosti,
> 
> I do agree with you that it is much easier and straight forward to change memory parameters when you are using the source agesa but it is definitely possible to do this for the binary agesa as well. You can provide the binary AGESA with external tables during run-time.
> 

Thanks Wim!

I can see how the relevant table that used to be in buildOPts.c is now implemented for DB-FT3b-LC board in agesawrapper.c.

So Wolfgang, you can pay for the development, which IMHO should not be more than 2 hours of engineering time, given the infrastructure is already there in binaryPI. Or request a free copy of the GPL'd DB-FT3b-LC coreboot OSP package from Sage (se-eng.com) to see for yourself where the table has to seat.

Or you can wait until DB-FT3b-LC board support appears upstreamed at coreboot.org. I have this board here on my desk so it might not take that long.

Regards,
Kyösti



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