[coreboot] [Rangeley C2000] Can't step when in romstage main function of MohonPeak

[郭佳]

Hi,

I'm debugging with Arium XDP3e debugger on ADI target board(MohonPeak based).
The coreboot.rom can bring target board up successfully in case of XDP
not plugged.
However, when stepping with debugger, the C code main function of romstage can't
be stepped, it always failed and the cpu goes into uncertain state.
The main function of C code is at src/southbridge/intel/fsp_rangeley/romstage.c.
At the time this main function has been called, the Cache as RAM has been setup
by FSP, and the MTRR_PHYSBASE0 is FEF0_0006.
The following is show in debugger:

void main(FSP_INFO_HEADER *fsp_info_header)
45                      {
main:
0008:FFC074E5 55               PUSH        EBP
0008:FFC074E6 89E5             MOV         EBP,ESP
0008:FFC074E8 56               PUSH        ESI
0008:FFC074E9 53               PUSH        EBX
0008:FFC074EA 83E4F0           AND         ESP,fffffff0
0008:FFC074ED 83EC20           SUB         ESP,00000020
46                       uint32_t pm1_cnt;
47                       uint16_t pm1_sts;
48                       uint32_t fd_mask = 0;
0008:FFC074F0 C744241C00000000 MOV         dword ptr [ESP]+1c,00000000

when step line 48: uint32_t fd_mask = 0, the cpu goes into uncertain state.
Since temporary stack has been setup, why should this instruction fail?
You can see the assembly form: MOV dword ptr [ESP] + 1c, 00000000,
The value of [ESP] + 1c is FEF03FDC, it's the cache region, and I can
even modify
this address in debugger's memory window, but it's wired that the
debugger can step
and go through :-(.

BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of
temporary stack are full of A5 5A, is it the correct case?
(2) When using debugger, does the PCH_Straps in SPI Flash descriptor executed as
normal start up case?

Please help me, thanks!

Sincerely,
Hook Guo