[coreboot] GCC update broke AMD Fam10h boot

Julius Werner jwerner at chromium.org
Fri Mar 20 03:21:37 CET 2015

> That said, I went back and looked at the assembly dump. It was using
> 0x14 as the size of the structure when sequencing through the entries.
> 001465dc R _bs_init_begin
> 001465e0 r cbmem_bscb
> 00146600 r gcov_bscb
> 0014663c R _bs_init_end
> Each *entry* was aligned to 0x20.  Just aligning the symbol wouldn't
> have fixed it. That means we'd need to mark the structure declaration
> as aligned to a specific value and annotate it accordingly in the
> linker script.  That's one route or just go w/ pointers to the
> structures.

Yeah, that's what I was talking about in the first mail... I think
this means that the compiler would consider the sizeof() for each
structure to be 0x20. I'm pretty sure there's some kind of rule that
the sizeof() for any object must be evenly divisible by its minimum
alignment... that's how normal arrays work as well (e.g. if you had
struct mystruct { uint32_t a; uint8_t b; } and don't mark it
__packed__, then sizeof(struct mystruct) is 0x8 and an array of them
would have 3 bytes padding after each entry). So I'm pretty sure the
pointer++ mechanism to walk through it would've still worked if the
initial address had been right. (can we repro this? then we could
simply try it out instead of guessworking.)

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