[coreboot] [Almost solved][Mohon Peak] Console output on external UARTs behind PCIe

Kyösti Mälkki kyosti.malkki at gmail.com
Sat Mar 14 12:31:26 CET 2015

On Fri, 2015-03-13 at 16:47 +0100, Patrick Agrain wrote:
> Hello,
> One step further !!
> I succeed to get it working.
> Several modification has to be made. I will try (next week) to get them 
> in a "readable form".
> - in ./src/device/pci_early.c:pci_early_bridge_init() :
> -- secondary = 1 for Mohon Peak.

The value of 'secondary' should not matter here, it does not need to
match with the value you later see in lspci.

> -- remove udelay() in PCI_VENDOR_ID reading (that's the big point). I 
> will try to have a look at it. Probably something very specific to this 
> chipset.

No clue about that.

> -- Put 'if (ret)' condition on the last 
> 'pci_bridge_set_secondary(p2p_bridge, 0);'.

Don't, as you would leave _some_ bridge claiming the bus number
'secondary', and PCI tree enumeration later in ramstage may try to
assign the same number to another bridge. If you find this is really
required, you would need to use a large value of 'secondary' to avoid
such a collision.

> - in ./src/drivers/uart/oxpcie_early.c:pci_early_device_probe() :
> -- uart1base is at CONFIG_EARLY_PCI_MMIO_BASE + 0x1200 for the Startech 
> board I have.

What PCI ID did your card report again? Different IDs will use different
resource mapping, I'll need to compare against the datasheet.

> BTW, I also included the patch covered by 
> http://review.coreboot.org/#/c/8660/. Compiler does not complain anymore 
> (and 'in fine' it works).

I have submitted iteration #2 of this change.

> Logs are now available from 'coreboot-<...> ramstage starting'.

Let's try to make it work from the ".. romstage starting" message.

> Thanks for your support.
> Regards,
> Patrick Agrain


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