[coreboot] [Mohon Peak] Console output on external UARTs behind PCIe

Patrick Agrain patrick.agrain at alcatel-lucent.com
Wed Mar 11 16:21:19 CET 2015

Hello Kyösti,

I tried what you suggested below:

- Set Bridge at D:1 F:0
- Enabled OXI PCIe952 and disabled SERIAL_PORT_ON_SUPERIO.
Reboot Mohon Peak CRB: failed. No output. POST code at 0xA9.

Will try to get further.
If anybody has an idea...

Patrick Agrain

On Fri, 2015-03-06 at 17:25 +0100, Patrick Agrain wrote:
>/  Hello everybody,
/>/  Do you think that it would be possible to output the console messages
/>/  from coreboot (seabios) on another UART port (strapped to be visible on
/>/  Memory-based space or IO Space) connected on a PCIe slot ?
Yes, it has been done before.

I should have a hack for SeaBIOS to support memory-mapped UART
somewhere, I will go and look. If I remember correctly SeaBIOS boot
media selection only works from local keyboard, not over serial.

>/  I've purchased a StarTech UART board with an OXPCIe952 chip, with the
/>/  same IDs as visible in ./src/drivers/uart/oxpcie.c.
/>/  On
/>/  http://www.coreboot.org/Serial_console#PCIe.2FMini_PCIe_based_serial_cards,  
/>/  what is behind the sentence:
/>/  "In order to use the card for romstage debugging, minimal setup of the
/>/  PCIe bridge and the MPEX2S952 have to be added to romstage.c" ?
You need to enable OxPCIe support and set EARLY_PCI_BRIDGE_* variables
in menuconfig. If you can boot to OS with that plaform, with the serial
card installed, get the location of PCIe rootport (aka. parent bridge)
for OxPCIe card with lspci -vv command.

Once you have OS shell, both coreboot and SeaBIOS console messages are
available from CBMEM console using 'cbmem -c' command.

>/  Thanks in advance.
/>/  Best regards,
/>/  Patrick Agrain



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