[coreboot] Minnowmax: Has anyone used the XDP debug port with coreboot?

Ben Gardner gardner.ben at gmail.com
Thu Dec 17 18:30:00 CET 2015

Hi Brett,

If you don't mind, I have a few more questions about your setup.

On Thu, Dec 17, 2015 at 10:25 AM, Testerman, Brett (US COM)
<Brett.Testerman at cobham.com> wrote:
> I have a custom E38xx design (Baytrail) that I ported Coreboot on to. XDP
> works fine but you must install the TXE image in the boot flash else the
> port is locked out.

We don't need secure boot, so we are chose the 'SLIM' TXE image.
Did you have to do anything to configure the TXE image, like setting

The Intel System Debugger indicates that the "JTAG connection was
established but the target appears to have security-restricted JTAG.
Please try disabling JTAG security in the platform firmware."
(That was with FSP Gold v3. I haven't yet tested with FSP Gold v4. The
XDP hardware is at another location, so testing is a bit difficult.)

Out Intel rep says that we have to send the "Set Debug State" FMI
command to the TXE engine to enable debug.
The problem I ran into with that is that the FspInitEntry (Goldv4)
call hides the TXE PCI device (1a.0) and it doesn't seem like I can
send a FMI command without RAM first being initialized.

Does any of that sound familiar? Or did it "just work" for your board?
I would expect it to "just work" if secure boot was disabled.

Last question about your gpio.c file:
It looks like GPIO_S5[22-30] are used for XDP.
Minnowmax has GPIO_S5[22] as GPIO_NC and GPIO_S5[23-30] set as

Is that how you configured the XDP-related pins?
If not, would you mind sending you gpio.c file so I can compare?


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