[coreboot] fwts MTRR tests fail on ASRock E350M1

[Aaron Durbin]

On Sat, Aug 8, 2015 at 11:54 PM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Dear coreboot folks,
>
>
> following Patrick to test devices with the Firmware Test Suite [1], I
> built fwts V15.08.00-7-g9ddce1f from the their Git repository [2] and
> ran it on the ASRock E350M1 with coreboot [3] and SeaBIOS.
>
> The first tests failing are the MTRR tests.
>
> ```
> mtrr: MTRR tests.
> --------------------------------------------------------------------------------
> MTRR overview
> -------------
> Reg 0: 0x0000000000000000 - 0x0000000080000000 (  2048 MB)   Write-Back
> Reg 1: 0x0000000080000000 - 0x00000000c0000000 (  1024 MB)   Write-Back
> Reg 2: 0x00000000c0000000 - 0x00000000c8000000 (   128 MB)   Write-Back
> Reg 6: 0x00000000ffc00000 - 0x0000000100000000 (     4 MB)   Write-Protect
>
> Test 1 of 3: Validate the kernel MTRR IOMEM setup.
> FAILED [MEDIUM] MTRRIncorrectAttr: Test 1, Memory range 0x100000000 to
> 0x21effffff (System RAM) has incorrect attribute Default (Most probably
> Uncached).
> FAILED [MEDIUM] MTRRLackingAttr: Test 1, Memory range 0x100000000 to 0x21effffff
> (System RAM) is lacking attribute Write-Back.

The E350M1 is an AMD system. On those systems there is a TOM2 msr to
cover memory above 4GiB as writeback. I don't know what family the
cores are in that system, however here is the BKDG link for family
10h: http://support.amd.com/TechDocs/31116.pdf

MSRC001_0010 System Configuration Register (SYS_CFG) bits:
22 Tom2ForceMemTypeWB: top of memory 2 memory type write back.
Read-write. 1=The default memory type of memory between 4GB and TOM2
is write back instead of the memory type defined by [The MTRR Default
Memory Type Register (MTRRdefType)] MSR0000_02FF[MemType]. For this
bit to have any effect, MSR0000_02FF[MtrrDefTypeEn] must be 1. MTRRs
and PAT can be used to override this memory type.

21 MtrrTom2En: MTRR top of memory 2 enable. Read-write. 0=[The Top Of
Memory 2 Register (TOM2)] MSRC001_001D is disabled. 1=This register is
enabled.

And the TOM2 msr:
MSRC001_001D Top Of Memory 2 Register (TOM2)
47:23 TOM2[47:23]: second top of memory. Read-write. Specifies the
address divides between MMIO and DRAM. This value is normally placed
above 4G. From 4G to TOM2 - 1 is DRAM; TOM2 and above is MMIO. See
2.9.3 [Access Type Determination]. This register is enabled by [The
System Configuration Register (SYS_CFG)] MSRC001_0010[MtrrTom2En].

If those settings are employed then I'd expect the MTRRs not to cover
memory above 4GiB.

>
> Test 2 of 3: Validate the MTRR setup across all processors.
> PASSED: Test 2, All processors have the a consistent MTRR setup.
>
> Test 3 of 3: Test for AMD MtrrFixDramModEn being cleared by the BIOS.
> PASSED: Test 3, No MtrrFixDramModEn error detected.
>
> ================================================================================
> 2 passed, 2 failed, 0 warning, 0 aborted, 0 skipped, 0 info only.
> ================================================================================
> ```
>
> I’ll try to look into it in the coming weeks, but if somebody has an
> idea and a suggestion for a fix, that would be great. Please also
> comment, if fwts is not correct in this regard.)
>
>
> Thanks,
>
> Paul
>
>
> [1] https://wiki.ubuntu.com/Kernel/Reference/fwts
> [2] git://kernel.ubuntu.com/hwe/fwts
> [3] commit 6de27da3 (samsung/exynos5250: Enable bootblock console)
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