[coreboot] New Defects reported by Coverity Scan for coreboot

scan-admin at coverity.com scan-admin at coverity.com
Sun Apr 5 15:41:20 CEST 2015


Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

9 new defect(s) introduced to coreboot found with Coverity Scan.
3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 9 of 9 defect(s)


** CID 1293141:  Integer handling issues  (CONSTANT_EXPRESSION_RESULT)
/src/soc/rockchip/rk3288/sdram.c: 1027 in sdram_init()


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*** CID 1293141:  Integer handling issues  (CONSTANT_EXPRESSION_RESULT)
/src/soc/rockchip/rk3288/sdram.c: 1027 in sdram_init()
1021     
1022     		if (sdram_params->dramtype == LPDDR3) {
1023     			/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1024     			udelay(10);
1025     			send_command(ddr_pctl_regs,
1026     				(sdram_params->ch[channel].rank | 1),
>>>     CID 1293141:  Integer handling issues  (CONSTANT_EXPRESSION_RESULT)
>>>     "(176 /* (0xb & 0xff) << 4 */) | sdram_params->odt" is always true regardless of the values of its operands. This occurs as the logical first operand of '?:'.
1027     				MRS_CMD, LPDDR2_MA(11) |
1028     				sdram_params->odt ? LPDDR2_OP(3) : 0);
1029     			if (channel == 0) {
1030     				writel(0, &ddr_pctl_regs->mrrcfg0);
1031     				send_command(ddr_pctl_regs, 1, MRR_CMD,
1032     					LPDDR2_MA(0x8));

** CID 1293140:  Control flow issues  (DEADCODE)
/src/soc/nvidia/tegra124/dp.c: 784 in tegra_dp_channel_eq_status()


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*** CID 1293140:  Control flow issues  (DEADCODE)
/src/soc/nvidia/tegra124/dp.c: 784 in tegra_dp_channel_eq_status()
778     	u8 ce_done = 1;
779     
780     	for (cnt = 0; cnt < n_lanes / 2; cnt++) {
781     		tegra_dc_dp_dpcd_read(dp, (NV_DPCD_LANE0_1_STATUS + cnt), &data);
782     
783     		if (n_lanes == 1) {
>>>     CID 1293140:  Control flow issues  (DEADCODE)
>>>     Execution cannot reach the expression "ce_done" inside this statement: "ce_done = data & 2 && data ...".
784     			ce_done = (data &
785     					(0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) &&
786     			(data &	(0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT));
787     			break;
788     		} else if (!(data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) ||
789     			!(data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) ||

** CID 1293139:  Control flow issues  (DEADCODE)
/src/soc/intel/broadwell/pcie.c: 112 in pcie_iosf_port_grant_count()


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*** CID 1293139:  Control flow issues  (DEADCODE)
/src/soc/intel/broadwell/pcie.c: 112 in pcie_iosf_port_grant_count()
106     
107     	switch (rpcd) {
108     	case 1:
109     	case 3:
110     		update_val = 0x02;
111     		break;
>>>     CID 1293139:  Control flow issues  (DEADCODE)
>>>     Execution cannot reach this statement: "case 2U:".
112     	case 2:
113     		update_val = 0x22;
114     		break;
115     	default:
116     		update_val = 0x00;
117     		break;

** CID 1293138:  Control flow issues  (DEADCODE)
/src/soc/nvidia/tegra124/dp.c: 815 in tegra_dp_clock_recovery_status()


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*** CID 1293138:  Control flow issues  (DEADCODE)
/src/soc/nvidia/tegra124/dp.c: 815 in tegra_dp_clock_recovery_status()
809     
810     	for (cnt = 0; cnt < n_lanes / 2; cnt++) {
811     		tegra_dc_dp_dpcd_read(dp,
812     			(NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);
813     
814     		if (n_lanes == 1)
>>>     CID 1293138:  Control flow issues  (DEADCODE)
>>>     Execution cannot reach the expression "data_ptr & 1" inside this statement: "return (data_ptr & 1) ? 1 : 0;".
815     			return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? 1 : 0;
816     		else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ||
817     			!(data_ptr &
818     			(NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES)))
819     			return 0;
820     	}

** CID 1293137:  Control flow issues  (MISSING_BREAK)
/src/soc/nvidia/tegra124/sor.c: 849 in tegra_dc_sor_set_voltage_swing()


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*** CID 1293137:  Control flow issues  (MISSING_BREAK)
/src/soc/nvidia/tegra124/sor.c: 849 in tegra_dc_sor_set_voltage_swing()
843     	case SOR_LINK_SPEED_G2_7:
844     		drive_current = 0x13131313;
845     		pre_emphasis = 0;
846     		break;
847     	case SOR_LINK_SPEED_G5_4:
848     		printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n");
>>>     CID 1293137:  Control flow issues  (MISSING_BREAK)
>>>     The above case falls through to this one.
849     	default:
850     		printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n",
851     			sor->link_cfg->link_bw);
852     		return;
853     	}
854     

** CID 1293136:  Control flow issues  (NESTING_INDENT_MISMATCH)
/src/arch/arm64/boot.c: 73 in arch_prog_run()


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*** CID 1293136:  Control flow issues  (NESTING_INDENT_MISMATCH)
/src/arch/arm64/boot.c: 73 in arch_prog_run()
67     {
68     	void (*doit)(void *);
69     	void *arg;
70     
71     	if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD)
72     		run_payload(prog);
>>>     CID 1293136:  Control flow issues  (NESTING_INDENT_MISMATCH)
>>>     This  statement is indented to column 17, as if it were nested within the preceding parent statement, but it is not.
73     		return;
74     
75     	doit = prog_entry(prog);
76     	arg = prog_entry_arg(prog);
77     
78     	doit(prog_entry_arg(prog));

** CID 1293135:  Incorrect expression  (NO_EFFECT)
/src/northbridge/amd/amdfam10/raminit_amdmct.c: 215 in amdmct_cbmem_store_info()


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*** CID 1293135:  Incorrect expression  (NO_EFFECT)
/src/northbridge/amd/amdfam10/raminit_amdmct.c: 215 in amdmct_cbmem_store_info()
209     {
210     	/* Save memory info structures for use in ramstage */
211     	size_t i;
212     	struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
213     	struct DCTStatStruc *pDCTstatA = NULL;
214     
>>>     CID 1293135:  Incorrect expression  (NO_EFFECT)
>>>     Comparing an array to null is not useful: "sysinfo->DCTstatA".
215     	if (pMCTstat && sysinfo->DCTstatA) {
216     		/* Allocate memory */
217     		struct amdmct_memory_info* mem_info;
218     		mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info));
219     		if (!mem_info)
220     			return;

** CID 1293134:  Uninitialized variables  (UNINIT)
/src/soc/intel/broadwell/pcie.c: 126 in root_port_init_config()


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*** CID 1293134:  Uninitialized variables  (UNINIT)
/src/soc/intel/broadwell/pcie.c: 126 in root_port_init_config()
120     	RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val;
121     }
122     
123     static void root_port_init_config(device_t dev)
124     {
125     	int rp;
>>>     CID 1293134:  Uninitialized variables  (UNINIT)
>>>     Declaring variable "data" without initializer.
126     	u32 data;
127     	u8 resp, id;
128     
129     	if (root_port_is_first(dev)) {
130     		rpc.orig_rpfn = RCBA32(RPFN);
131     		rpc.new_rpfn = rpc.orig_rpfn;

** CID 1293133:  Control flow issues  (UNREACHABLE)
/src/arch/arm64/boot.c: 75 in arch_prog_run()


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*** CID 1293133:  Control flow issues  (UNREACHABLE)
/src/arch/arm64/boot.c: 75 in arch_prog_run()
69     	void *arg;
70     
71     	if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD)
72     		run_payload(prog);
73     		return;
74     
>>>     CID 1293133:  Control flow issues  (UNREACHABLE)
>>>     This code cannot be reached: "doit = prog_entry(prog);".
75     	doit = prog_entry(prog);
76     	arg = prog_entry_arg(prog);
77     
78     	doit(prog_entry_arg(prog));


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