[coreboot] [RFT] Please test patch set intel/i945: Only write CID, PN and TCID once

ron minnich rminnich at gmail.com
Sun Mar 16 23:38:53 CET 2014

First, Mono, thank *you* for your interest and involvement in coreboot.

On Sun, Mar 16, 2014 at 2:00 PM, Mono <mono at posteo.de> wrote:

> Moreover, I was not aware that the code might do something else than what
> one can know by reading the code and the public documentation. To be
> honest, if that was true, I would be disappointed, because I expected
> coreboot to be a possibility of getting away from private software and "you
> don't know what your machine does".

Yeah, if only it were this simple ::-)
It was, at some point, but The Empire Struck Back.

> At the moment I believe that applying the patch does no harm. At least
> this is my current knowledge by running it at the MacBook2,1 for a couple
> of hours. Switching forth and back between coreboot versions (back to safe
> ones) works. I do not know if this was true for other boards.
Yes, your test is just not a sufficient test. There's a fair amount of
systems out there with this chipset. It's easy to create code that works on
*your* version of the macbook with *your* rev of the chipset. But what if
it breaks an older version, and we don't know for a year until someone
reports that his getac just broke? This happens and it's very painful. So
the rule is not to change things unless you know it fixes a bug -- and you
really need to document that bug.

The problem solving flowchart is very helpful here.


Here's a true story. We once had a 256-or-so node cluster at LANL. Same
vendor, same server node, same mainboards, same chipset, 1/2 the boards ran
at 15% lower PCI speed than the other half. All chipsets had the same PCI
devid, same rev. What was different? We finally got to realizing that 1/2
the chipsets were made at one fab, half another. And that was the reason.

It's very subtle at the lower levels.

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