[coreboot] I've turned on paging as a test

Aaron Durbin adurbin at chromium.org
Tue Mar 11 06:40:53 CET 2014


On Mon, Mar 10, 2014 at 9:02 PM, ron minnich <rminnich at gmail.com> wrote:
> Looking at the table, it seems to me that one can set an MTRR for a very
> large area, to WB, and then have very fine control (4k boundaries, or 2M, or
> 1G [I've used 1G before]) over the types of caching actually used as well as
> protections. See figure 11-7, and see what you think.
>
> If this were true, then it might make our MTRR life a whole lot easier.

That's definitely possible. One just needs to ensure that paging is
always enabled if you were going to employ this approach.

>
> ron
>
>
> On Mon, Mar 10, 2014 at 5:36 PM, Aaron Durbin <adurbin at google.com> wrote:
>>
>> On Mon, Mar 10, 2014 at 5:32 PM, ron minnich <rminnich at gmail.com> wrote:
>> > I'm *pretty* *sure* that you can use the PATs as an alternative to
>> > MTRRs. I
>> > am going to dig a bit. It would sure make our life easier if we could
>> > live
>> > without all this MTRR fuss. We keep having to tweak the code and it's
>> > never
>> > been fun.
>> >
>> > And I like the idea of write-protecting coreboot code.
>>
>> In Intel manuals, there's a table named "Effective Page-Level Memory
>> Types for Pentium III and More Recent Processor Families." There's a
>> table that lists the combination of PAT and MTRR. It's not a an
>> alternative. It describes how those settings interact.
>>
>> Anyway, depending on what exactly you want to solve there may be other
>> solutions to your problem.
>>
>> -Aaron
>
>



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