[coreboot] I've turned on paging as a test

ron minnich rminnich at gmail.com
Tue Mar 11 01:41:12 CET 2014

Ah well, too bad. This CL may end up as an historical curiousity.

But that said most OSes I've work on last 10 years use PTEs for lots of
this control. I'll check out that table.


On Mon, Mar 10, 2014 at 5:36 PM, Aaron Durbin <adurbin at google.com> wrote:

> On Mon, Mar 10, 2014 at 5:32 PM, ron minnich <rminnich at gmail.com> wrote:
> > I'm *pretty* *sure* that you can use the PATs as an alternative to
> MTRRs. I
> > am going to dig a bit. It would sure make our life easier if we could
> live
> > without all this MTRR fuss. We keep having to tweak the code and it's
> never
> > been fun.
> >
> > And I like the idea of write-protecting coreboot code.
> In Intel manuals, there's a table named "Effective Page-Level Memory
> Types for Pentium III and More Recent Processor Families." There's a
> table that lists the combination of PAT and MTRR. It's not a an
> alternative. It describes how those settings interact.
> Anyway, depending on what exactly you want to solve there may be other
> solutions to your problem.
> -Aaron
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