[coreboot] coreboot on amd A85 can't work

Scott Duplichan scott at notabs.org
Fri Mar 7 05:08:54 CET 2014

陈军根 [mailto:cjg at bolod.net]  wrote:

]Hello Rudolf:
]Because coreboot can't work in F2A85-MLE, I buy a new mainboard
]f2a85-M,and coreboot can run ok in my f2a85-m, also can boot
]ubuntu.But I find a strange question: when I plug my DIMM in
]DIMM_A1 or DIMM_B1, coreboot can't work, and get the error messages
]"assertion Failed:file
]'src/vendorcode/amd/agesa/f15tn/proc/mem/main/mmexcludedimm.c',line 236".
]but when I plug my DIMM in DIMM_A2 or DIMM_B2, coreboot work well;
]Did coreboot only support DIMM_A2 or DIMM_B2 in F2A85-M?

>From my reading of the F2A85-M manual, the preferred slot for
a single DIMM is DIMM_A2. So this coreboot behavior doesn't seem
bad. A few years ago, AMD changed the DIMM population order from
a recommendation to a requirement. It may be that Asus reversed
that change for their ROMs.

]I think this is also the reason why coreboot can't work in F2A85-MLE.
]Because F2A85-MLE only have DIMM_A1 and DIMM_B1.

You are probably correct. Because F2A85-MLE has only one DIMM
per channel, you need this change:

diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 0091cd9..73a0a8c 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -439,7 +439,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   //      Speicifes the HW RXEN training seed for a channel of a socket
   TODO: is this OK for DDR3 socket FM2?

For completeness, the F2A85-MLE code should also have this change:
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 0014381..97316d6 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -122,7 +122,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
 			register "spdAddrLookup" = "
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
 				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses

This should work, assuming F2A85-MLE uses SPD addresses A0 and A2.
If not, adjust as needed.

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