[coreboot] Intel FSP on Bayley Bay CRB
marcj303 at gmail.com
Tue Jun 10 22:04:19 CEST 2014
Does the crb have a port80? You should get early postcodes from
coreboot and the FSP. You are also correct that there might be
something different in the descriptor.bin that isn't anticipated. You
may want to use the coreboot util/ifdtool to get a look at the entire
On Tue, Jun 3, 2014 at 6:03 AM, Gerald Otter <gerald.otter at gmail.com> wrote:
> Hi all,
> I am trying to run coreboot + seabios payload on the bayley bay crb with the recently committed FSP integration, but have had no luck so far.
> This crb uses the bay trail I (now atom e3800) soc from intel.
> Following the instructions from commit d75800c7f , I have built a 2MB image and flashed it to the upper 2MB of the 8MB flash, leaving the TXE / flash descriptor intact.
> I have added the config from the build. The FSP I used is BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014, together with the flash descriptor and TXE from the 80.21 bios provided by intel, and vga bios 36.2.2.
> Fwiw, I have tried both the 32bit and 64bit releases of the bios, even though the flash descriptor and TXE binary seem to be exactly the same.
> The issue I’m running into is that I have no idea if anything is running at all.
> There is no output on the VGA/HDMI ports or uart.
> The legacy uart referred to in the source is working correctly with the original intel bios, but does not produce any output with the coreboot image.
> I have tried the most common baud rates (115200, 19200, 9600 ) and did some measurements with a scope in case I got the baud rate wrong, but no cigar.
> The uart I’m using is the PCU uart, as opposed to hsuart1/2 and the superIO uart. This matches with the configuration in coreboot when compared to the datasheet, so I’m assuming I got this set up correctly.
> Unfortunately, this is about all the information I have, so I hope I am missing something obvious when building the image / flashing it, etc.
> I have also used intel’s flash image tool (fitc) to build a complete image, thinking that maybe the flash descriptor needed to contain some specific information regarding the coreboot image (size/checksums), but given the original instructions I wasn’t surprised this didn’t work.
> Thanks in advance!
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