[coreboot] smi handler support for fsp baytrail

Sun, Jiming jiming.sun at intel.com
Fri Jun 6 18:15:28 CEST 2014

Hi, Tank,

It might be the TSEG size configuration.

In devicetree.cb:
    register "MrcInitTsegSize"      = "TSEG_SIZE_DEFAULT"

By default  TSEG_SIZE_DEFAULT is 0.   It needs to be set to none 0, such as 8  (TSEG_SIZE_8_MB).

Let us know if this helps.


From: jstkf2012 at 126.com [mailto:jstkf2012 at 126.com]
Sent: Thursday, June 05, 2014 11:48 PM
To: coreboot
Cc: martin.roth; rminnich
Subject: [coreboot] smi handler support for fsp baytrail

Hi all,

    What about the smi support for fsp baytrail?When I select HAVE_SMI_HANDLER for fsp baytrail,it will halt at:
    ERROR: Could not find FSP HOB pointer in CBFS!
    POST: 0x79
    POST: 0x9c
    ACPI: Writing ACPI tables at f0000.
    ACPI: * FACS @ 000f0210 Length 40ACPI: * DSDT @ 000f0250 Length 2a89SCI is IRQ9
    ACPI: added table 1/32, length now 40
    ACPI: * FADT @ 000f2ce0 Length f4ACPI: added table 2/32, length now 44
    ACPI: * HPET @ 000f2de0 Length 38
    ACPI: added table 3/32, length now 48
    ACPI: * MADT @ 000f2e20 Length 6c
    ACPI: added table 4/32, length now 52
    ACPI: * MCFG @ 000f2e90 Length 3c
    ACPI: Could not find CBMEM GNVS
    ACPI: Patching up global NVS in DSDT at offset 0x009f -> 000f2ed0

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