[coreboot] Intel FSP on Bayley Bay CRB: No output
martin.roth at se-eng.com
Fri Jun 6 00:39:45 CEST 2014
Eh, it's code... It's going to have issues and bugs. We're all
interested in getting these things to the highest quality, and we're all
working to that end. It'll get better as it goes along. They're still
actively developing the code and working to improve things, so in that
way it's definitely better than getting a single source code drop that
never gets updated again. Intel will have another Bay Trail FSP release
out shortly that will hopefully address this issue.
On 06/05/2014 02:43 PM, Peter Stuge wrote:
> Martin Roth wrote:
>> the FSP is supposed to
> It looks very bad when FSP shortcomings generate issues in coreboot.
> I can only hope that the whole FSP thing was in fact exceptionally
> well thought through...
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