[coreboot] IMB-A180 based design - help with post codes

Dave Frodin dave.frodin at se-eng.com
Mon Jun 2 22:24:36 CEST 2014

I captured a port 80 log from a design similar to the IMB-a180 board and it
looks identical.
My guess (if what you are hoping to see is graphics output) is that the
graphics PCI ID doesn't
match the vga bios ID. We normally let seabios load the video bios. Maybe
you could add some
code to dump out the graphics device ID for device 0:1.0. On my system I
get 1002:9835. The
video bios rom image in CBFS would need that ID in it, or the rom would
need to be stored in
CBFS in the generic "vgaroms/" folder (e.g. vgaroms/my_vbios.rom).


On Fri, May 30, 2014 at 1:50 PM, Kyösti Mälkki <kyosti.malkki at gmail.com>

> On 05/30/2014 09:19 PM, Mark C. Mason wrote:
>> We are bringing up a modified IMB-A180 design, and coreboot appears
>> to be running off the rails (resets to 0xfffffff0 consistently).
>> There is only one dimm in the 0 socket, so NUMBER_DIMMS_SUPPORTED
>> is 1 in buildOpts.c, and devicetree.cb has only i2c address 0xA0.
>> This appears to work.
>> There is no superIO, and hence no serial port (yet; I will add a USB
>> based debugger soon),
>> and this has been removed from devicetree.cb.
>> I'm in the process of finding and mapping all the post codes, but
>> any wisdom from the community would be appreciated at this point.
>> The post codes are below; it appears to be getting pretty far along
>> (though I am
>> new to  coreboot and this may be optimistic).
>> The questions I have are:
>>      - what is going on at the end?
>>      - has dimm memory been successfully configured and is in use?
>>      - should the vga console be functional at this time?  (no sign of
>> life there)
>> It always resets to 0xfffffff0 at the same point at the end of the post
>> codes.
>> Thanks in advance,
>> Mark Mason
>> Engineering Design Team
>  0004600 55 64 e2 e3 65 ab e2 e3 e6 e7 cd ff e2 e3 ce e6
>> 0004620 e6 e6 e7 ec e2 e3 ed e6 e7 b8 cf e6 e7 e4 e4 e5
>> 0004640 e4 e5 9b 9c 9e 9d 7a 7b f8
>> 0004651
> Decode the last three with this:
>    src/include/console/post_codes.h
> Seems to be loading and jumping to payload. Note that some payloads
> configurations will hit watchdog and reset in 60 seconds if they cannot
> find boot media.
> You can apply the attached patch as a quick hack I recently made to send
> coreboot console text to IO port 0x3f8 without any actual UART hardware.
> If necessary, you can also disable any POST displays in menuconfig, and
> change this patch to use IO 0x80. But listening on IO 0x3f8 may give you
> output from payload too.
> I'd recommend the USB debug method for any further serious work.
> Kyösti
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
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