[coreboot] Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0

Oliver Schinagl oliver+list at schinagl.nl
Sat Jan 25 12:01:39 CET 2014


Nobody interested at all?

I've since found that I can cut them more then adequatly with an 
metal-saw and is much faster then using a break-away-knife. SO i should 
have 80 adapters at FOSDEM.

You reccon it's better to give them away? or sell them for 50c - 1e? 
This to prevent people from just randomly grabbing them cause its free 
stuff and not actually even remotely intend to actually use them.

Oliver

On 01/19/14 18:45, Olliver Schinagl wrote:
> Hi coreboot!
>
> I finally sent off my order to seeed and have received the boards back.
> It turns out, that over the last year (and a half) seeed actually
> improved their processes and have even narrower minimals, which is great
> for this board.
>
> Anyway, I took some pics and the uploaded the schematics to [1]. I
> rather host the schematics etc somewhere on coreboot's servers, as I
> feel this is as use full to coreboot as anything else.
>
> The only thing I'm not so happy about is the footprint of the FET
> switch. The legs don't seem to match up perfectly (the outer ones only
> strangely) and the pads should have been bigger to make soldering
> easier. But since it is optional (if you bridge s1 and s2 the chip
> doesn't have to be mounted, nor does RN1 I think, but it's been a while :p)
>
> I haven't split all of the boards yet, but I should have tons! 12 * 8. I
> am attending FOSDEM2014 so if any of the coreboot folk are having a
> booth or even just attending, I'd be happy to bring the boards along so
> they can be gifted. Anybody able to cut them though? I used a stanley
> knife scorching the board but that took quite some time :) Using a
> dremel requires extremely steady hands, as the cutting wheel probably
> does fit, but it's extremely tight.
>
> Anyway, looking forward to show it all off @FOSDEM2014 ;)
>
> oliver
>
> [1] http://oliver.schinagl.nl/gallery/v/geek_stuff/dspif/
>
> Quoted the below to help remind people what this post is really about ;)
>
> On 05/13/12 15:39, Oliver Schinagl wrote:
>> Just an FYI,
>>
>> This is the final version that I will send over to seeed after placing
>> an order. The only thing that will change is the order number (now it's
>> an arbitrary number). If I have to do major changes to the board, I will
>> of course send an updated version to the list.
>>
>> Oliver
>>
>> On 04/28/12 16:14, Oliver Schinagl wrote:
>>> Hey all,
>>>
>>> Find here all included fixes and modifications. I've increased spacing
>>> and removed the 'outline' layer. I moved parts to the edge. Since Seeed
>>> does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
>>> is ...
>>>
>>> If I don't see any feedback on things that need fixing here, I'll set
>>> out an order for the prototypes :)
>>>
>>> Oliver
>>>
>>> Have a good weekend all!
>>>
>>> On 04/26/12 18:56, Oliver Schinagl wrote:
>>>> Hey all,
>>>>
>>>> Well here it is, the last version which was even harder then the 3rd
>>>> one. or so it seemed anyhow.
>>>>
>>>> I will work on copying these four to the bottom and renaming the labels
>>>> before sending them off. I'll post the final pcb on this list again,but
>>>> routing wise, Nothing will change, unless of course someone found a
>>>> grand mistake.
>>>>
>>>> So really, all input is greatly appreciated :D would be shameful to send
>>>> this off to get printed, just to find bugs and have another batch made.
>>>>
>>>> Oliver
>>>>
>>>> On 23-04-12 20:23, Oliver Schinagl wrote:
>>>>> Hi!
>>>>>
>>>>> I've worked on a rotated version and planning to do two other
>>>>> orientations as well, so early feedback is good, so I don't have to
>>>>> redo them again :)
>>>>>
>>>>> Silk screening isn't 100% right, since I still need to rename them
>>>>> eventually somehow (edit .pcb file directly is probably the easiest
>>>>> way?)
>>>>>
>>>>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>>>>> Hi list(s),
>>>>>>
>>>>>> Here's my second attempt at routing the previously mailed png of my
>>>>>> schema.
>>>>>>
>>>>>> It was a lot trickier to route then my previous version, but I think it
>>>>>> worked out!
>>>>>>
>>>>>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>>>>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>>>>
>>>>>> Hopefully there's no obvious mistakes and can start working on
>>>>>> alternative layouts (so it is insert-able in different angles).
>>>>>>
>>>>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>>>>>> That said, DRC check passes when I set the copper width/distance to
>>>>>> 7mil's instead of the current 8 mils.
>>>>>>
>>>>>> I'm planning on having these PCB's manufactured by Seeed studio and
>>>>>> their minimal width is much smaller.
>>>>>>
>>>>>> Minimum trace width: 6mil
>>>>>> Minimum trace/vias/pads space : 6mil
>>>>>> Minimum silkscreen width : 4mil
>>>>>> Minimum silkscreen text size : 32mil
>>>>>>
>>>>>> I've used a grid size of 10mil and distances of 8 mils, as I didn't
>>>>>> want
>>>>>> to rely on the minimum of seed. The silkscreen I positioned using a
>>>>>> grid
>>>>>> size of 5 mil's however. Not sure what they mean with a 'minimum
>>>>>> silkscreen text size' however.
>>>>>>
>>>>>> Anyhow, feedback greatly appreciated, so I can start working on
>>>>>> alternative layouts :)
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>>
>>>
>>>
>>>
>>>
>
>




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