[coreboot] Pavilion Chromebook 14 (Butterfly) Q&A session
david.c.hubbard+coreboot at gmail.com
Mon Jan 20 20:36:22 CET 2014
On Mon, Jan 20, 2014 at 11:48 AM, mrnuke <mr.nuke.me at gmail.com> wrote:
> On Monday, January 20, 2014 12:37:30 PM you wrote:
> > I have some questions about this little guy. Fear not, your answers will
> > ported to the coreboot wiki at my earliest convenience.
> > 1. What is the maximum amount of RAM that it supports? Can in take in 2 x
> > 8GiB modules? If so, are there any limitations as to the number of ranks?
> > 2. Are the slots dual channel, or are both slots routed to same channel?
> > (From the source, I think it's dual.)
> > 3. If I install 1.35 V capable DIMMs, will coreboot run them at 1.35 V,
> > is 1.5 V the only option?
> > 4. If ECC modules are installed, will coreboot be able to enable ECC, or
> > those pins not even routed ?
> > 5. Why is SATA speed limited to 6Gbps (see devicetree.cb) ? From my
> > understanding, the first SATA port on the chipset is 6G capable, as is
> > SSD shipping inside. Is this a board routing limitation, or copypasta? I
> > can submit a patch if it's the latter.
Is this a typo? Did you mean the SATA is speed limited to 3Gbps?
> 6. Why is the max_ddr3_freq declared as 1600MHz when Intel's product page
> claims the CPU can do 1333 Max. Copypasta, or truly 1600 MHz capable ?
>  http://ark.intel.com/products/56056/
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