[coreboot] Trouble with coreboot for Roda RK9 (SOLVED)

Vladimir 'φ-coder/phcoder' Serbinenko phcoder at gmail.com
Fri Feb 14 14:23:21 CET 2014

On 14.02.2014 13:38, Dmitry Bagryanskiy wrote:
> //Enable Com3
> pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c02e1);
> //Enable Com4
> pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x001c03e1);
GEN*_DEC should not be set to com* ports. Instead there are dedicated
bits for enabling decode of serial port ranges. Consult southbridge

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